ispPAC-POWR1014-01T48I Lattice, ispPAC-POWR1014-01T48I Datasheet - Page 39

• Manufacturer Part Number: ispPAC-POWR1014-01T48I
• Description: Supervisory Circuits Prec. Prog. Pwr Sppl y Seq. Mon. Trim I
• Manufacturer: Lattice
• Series: ispPAC®r

Specifications of ispPAC-POWR1014-01T48I

• Number Of Voltages Monitored: 10
• Output Type: Open Collector / Drain
• Manual Reset: Not Resettable
• Watchdog: No Watchdog
• Power-up Reset Delay (typ): 500 ms
• Supply Voltage (max): 3.96 V
• Supply Voltage (min): 2.8 V
• Supply Current (typ): 20 mA
• Mounting Style: SMD/SMT
• Package / Case: TQFP-48
• Applications: General Purpose
• Voltage - Input: -0.3 V ~ 5.9 V
• Voltage - Supply: 2.8 V ~ 3.96 V
• Current - Supply: 20mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: *
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
ified. Table 2-11 lists the instructions supported by the ispPAC-POWR1014/A JTAG Test Access Port (TAP) control-
ler.
Table 2-11. ispPAC-POWR1014/A TAP Instruction Table
BYPASS is one of the three required instructions. It selects the Bypass Register to be connected between TDI and
TDO and allows serial data to be transferred through the device without affecting the operation of the ispPAC-
POWR1014/A. The IEEE 1149.1 standard defines the bit code of this instruction to be all ones (11111111).
The required SAMPLE/PRELOAD instruction dictates the Boundary-Scan Register be connected between TDI
and TDO. The ispPAC-POWR1014/A has no boundary scan register, so for compatibility it defaults to the BYPASS
mode whenever this instruction is received. The bit code for this instruction is defined by Lattice as shown in
Table 2-11.
BULK_ERASE
BYPASS
DISCHARGE
ERASE_DONE_BIT
I2C_DATA_REGISTER
I2C_CONTROL_REGISTER
EXTEST
IDCODE
OUTPUTS_HIGHZ
SAMPLE/PRELOAD
PROGRAM_DISABLE
PROGRAM_DONE_BIT
PROGRAM_ENABLE
PROGRAM_SECURITY
RESET
IN1_RESET_JTAG_BIT
IN1_SET_JTAG_BIT
CFG_ADDRESS
CFG_DATA_SHIFT
CFG_ERASE
CFG_PROGRAM
CFG_VERIFY
PLD_ADDRESS_SHIFT
PLD_DATA_SHIFT
PLD_INIT_ADDR_FOR_PROG_INCR
PLD_PROG_INCR
PLD_PROGRAM
PLD_VERIFY
PLD_VERIFY_INCR
UES_PROGRAM
UES_READ
Instruction
Command Code
0000 0011
1111 1111
0001 0100
0010 0100
0010 0101
0010 0110
0000 0000
0001 0110
0001 1000
0001 1100
0001 1110
0010 1111
0001 0101
0000 1001
0010 0010
0001 0010
0001 0011
0010 1011
0010 1101
0010 1001
0010 1110
0010 1000
0000 0001
0000 0010
0010 0001
0010 0111
0000 0111
0000 1010
0010 1010
0001 1010
0001 0111
2-39
Bulk erase device
Bypass - connects TDO to TDI
Fast VPP discharge
Erases ‘Done’ bit only
Accessing I
Controls read and write functions of I
Bypass - connect TDO to TDI
Read contents of manufacturer ID code (32 bits)
Force all outputs to High-Z state, FET outputs pulled low
Sample/Preload. Default to bypass.
Disable program mode
Programs the Done bit
Enable program mode
Program security fuse
Resets device (refer to the RESETb Signal, RESET Com-
mand via JTAG or I2C section of this data sheet)
Reset the JTAG bit associated with IN1 pin to 0
Set the JTAG bit associated with IN1 pin to 1
Select non-PLD address register
Non-PLD data shift
ERASE just the non-PLD configuration
Non-PLD program
VRIFY non-PLD fusemap data
PLD_Address register (109 bits)
PLD_Data register (123 bits)
Initialize the address register for auto increment
Program column register to E
register
Program PLD data register to E
Verifies PLD column data
Load column register from E
register
Program UES bits into E
Read contents of UES register from E
2
C data register through JTAG (72 bits)
ispPAC-POWR1014/A Data Sheet
Comments
2
2
2
and auto increment address
and auto increment address
2
2
C registers (12 bits)
2
(32 bits)