ispPAC-POWR1014-01T48I Lattice, ispPAC-POWR1014-01T48I Datasheet - Page 37

• Manufacturer Part Number: ispPAC-POWR1014-01T48I
• Description: Supervisory Circuits Prec. Prog. Pwr Sppl y Seq. Mon. Trim I
• Manufacturer: Lattice
• Series: ispPAC®r

Specifications of ispPAC-POWR1014-01T48I

• Number Of Voltages Monitored: 10
• Output Type: Open Collector / Drain
• Manual Reset: Not Resettable
• Watchdog: No Watchdog
• Power-up Reset Delay (typ): 500 ms
• Supply Voltage (max): 3.96 V
• Supply Voltage (min): 2.8 V
• Supply Current (typ): 20 mA
• Mounting Style: SMD/SMT
• Package / Case: TQFP-48
• Applications: General Purpose
• Voltage - Input: -0.3 V ~ 5.9 V
• Voltage - Supply: 2.8 V ~ 3.96 V
• Current - Supply: 20mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: *
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
output, and related operations. Device programming is performed by addressing the configuration register, shifting
data in, and then executing a program configuration instruction, after which the data is transferred to internal
E
instructions are defined that access all data registers and perform other internal control operations. For compatibil-
ity between compliant devices, two data registers are mandated by the IEEE 1149.1 specification. Others are func-
tionally specified, but inclusion is strictly optional. Finally, there are provisions for optional data registers defined by
the manufacturer. The two required registers are the bypass and boundary-scan registers. Figure 2-30 shows how
the instruction and various data registers are organized in an ispPAC-POWR1014/A.
Figure 2-30. ispPAC-POWR1014/A TAP Registers
TAP Controller Specifics
The TAP is controlled by the Test Clock (TCK) and Test Mode Select (TMS) inputs. These inputs determine
whether an Instruction Register or Data Register operation is performed. Driven by the TCK input, the TAP consists
of a small 16-state controller design. In a given state, the controller responds according to the level on the TMS
input as shown in Figure 2-31. Test Data In (TDI) and TMS are latched on the rising edge of TCK, with Test Data
Out (TDO) becoming valid on the falling edge of TCK. There are six steady states within the controller: Test-Logic-
Reset, Run- Test/Idle, Shift-Data-Register, Pause-Data-Register, Shift-Instruction-Register and Pause-Instruction-
Register. But there is only one steady state for the condition when TMS is set high: the Test-Logic-Reset state. This
allows a reset of the test logic within five TCKs or less by keeping the TMS input high. Test-Logic-Reset is the
power-on default state.
2
CMOS cells. It is these non-volatile cells that store the configuration or the ispPAC-POWR1014/A. A set of
TDI
TEST ACCESS PORT (TAP)
CFG ADDRESS REGISTER (12 BITS)
I
INSTRUCTION REGISTER (8 BITS)
2
ADDRESS REGISTER (109 BITS)
C CONTROL REGISTER (12 BITS)
CFG DATA REGISTER (56 BITS)
TCK
I
IDCODE REGISTER (32 BITS)
2
DATA REGISTER (123 BITS)
C DATA REGISTER (72 BITS)
BYPASS REGISTER (1 BIT)
UES REGISTER (32 BITS)
LOGIC
TMS
2-37
OUTPUT
LATCH
TDO
ispPAC-POWR1014/A Data Sheet
NON-VOLATILE
MEMORY
E
2
CMOS