ispPAC-POWR1014-01T48I Lattice, ispPAC-POWR1014-01T48I Datasheet - Page 27

• Manufacturer Part Number: ispPAC-POWR1014-01T48I
• Description: Supervisory Circuits Prec. Prog. Pwr Sppl y Seq. Mon. Trim I
• Manufacturer: Lattice
• Series: ispPAC®r

Specifications of ispPAC-POWR1014-01T48I

• Number Of Voltages Monitored: 10
• Output Type: Open Collector / Drain
• Manual Reset: Not Resettable
• Watchdog: No Watchdog
• Power-up Reset Delay (typ): 500 ms
• Supply Voltage (max): 3.96 V
• Supply Voltage (min): 2.8 V
• Supply Current (typ): 20 mA
• Mounting Style: SMD/SMT
• Package / Case: TQFP-48
• Applications: General Purpose
• Voltage - Input: -0.3 V ~ 5.9 V
• Voltage - Supply: 2.8 V ~ 3.96 V
• Current - Supply: 20mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: *
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
Table 2-7. I
Several registers are provided for monitoring the status of the analog inputs. The three registers
VMON_STATUS[0:2] provide the ability to read the status of the VMON output comparators. The ability to read
both the ‘a’ and ‘b’ comparators from each VMON input is provided through the VMON input registers. Note that if
a VMON input is configured to window comparison mode, then the corresponding VMONxA register bit will reflect
the status of the window comparison.
Figure 2-18. VMON Status Registers
It is also possible to directly read the value of the voltage present on any of the VMON inputs by using the ispPAC-
POWR1014A’s ADC. Three registers provide the I
1. These registers can also be accessed through the JTAG interface.
2. “X” = Non-functional bit (bits read out as 1’s).
3. “–” = State depends on device configuration or input status.
Register
Address
0x0C
0x0D
0x0A
0x0B
0x0E
0x0F
0x00
0x01
0x02
0x03
0x04
0x06
0x07
0x08
0x09
0x11
0x12
2
C Control Registers
adc_value_high
output_status0
output_status1
adc_value_low
vmon_status0
vmon_status1
vmon_status2
input_status
UES_byte0
UES_byte1
UES_byte2
UES_byte3
gp_output1
gp_output2
input_value
Register
adc_mux
Name
0x00 - VMON_STATUS0 (Read Only)
0x01 - VMON_STATUS1 (Read Only)
0x02 - VMON_STATUS2 (Read Only)
reset
VMON4B
VMON8B
b7
b7
b7
1
VMON4A
VMON8A
Read/Write
b6
b6
b6
1
1
R/W
R/W
R/W
R/W
W
R
R
R
R
R
R
R
R
R
R
R
R
VMON3B
VMON7B
b5
b5
b5
1
VMON input status Vmon[4:1]
VMON input status Vmon[8:5]
VMON input status Vmon[10:9]
Output status OUT[8:3], HVOUT[2:1]
Output status OUT[14:9]
Input status IN[4:1]
ADC D[3:0] and status
ADC D[9:4]
ADC Attenuator and MUX[3:0]
UES[7:0]
UES[15:8]
UES[23:16]
UES[31:24]
GPOUT[8:1]
GPOUT[14:9]
PLD Input Register [4:2]
Resets device on write
VMON3A
VMON7A
2
C interface to the ADC (Figure 2-19).
b4
b4
b4
1
2-27
Description
VMON10B
VMON2B
VMON6B
b3
b3
b3
VMON10A
VMON2A
VMON6A
b2
b2
b2
ispPAC-POWR1014/A Data Sheet
VMON1B
VMON5B
VMON9B
b1
b1
b1
VMON1A
VMON5A
VMON9A
Value After POR
X X X X 0 0 0 X
X X X X – – – –
X X X X – – – –
– – – – X X X 1
X X X 1 1 1 1 1
X X – – – – – –
X X – – – – – –
X X 0 0 0 0 0 0
– – – – – – – –
– – – – – – – –
– – – – – – – –
– – – – – – – –
– – – – – – – –
– – – – – – – –
– – – – – – – –
0 0 0 0 0 1 0 0
b0
b0
b0
N/A
2, 3