ISP1761BE STEricsson, ISP1761BE Datasheet - Page 105

• Manufacturer Part Number: ISP1761BE
• Manufacturer: STEricsson

Specifications of ISP1761BE

• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: LQFP
• Rad Hardened: No
• Lead Free Status / Rohs Status: Supplier Unconfirmed

NXP Semiconductors
Table 98.
ISP1761_5
Product data sheet
Bit
Symbol
Reset
Bus reset
Access
Address register (address 0200h) bit allocation
10.5.1 Address register
unchanged
DEVEN
R/W
7
0
Table 97.
This register sets the USB assigned address and enables the USB peripheral.
shows the bit allocation of the register.
The DEVADDR[6:0] bits will be cleared whenever a bus reset, a power-on reset or a soft
reset occurs. The DEVEN bit will be cleared whenever a power-on reset or a soft reset
occurs, and will remain unchanged on a bus reset.
In response to standard USB request SET_ADDRESS, firmware must write the (enabled)
peripheral address to the Address register, followed by sending an empty packet to the
host. The new peripheral address is activated when the peripheral receives
acknowledgment from the host for the empty packet token.
Address Register
0228h
0220h
021Ch
021Eh
0204h
0208h
DMA registers
0230h
0234h
0238h
023Ch
0250h
0254h
0258h
0264h
General registers
0218h
0270h
0274h
0278h
027Ch
0280h
0284h
R/W
6
0
0
Control Function
Data Port
Buffer Length
DcBufferStatus
Endpoint MaxPacketSize
Endpoint Type
DMA Command
DMA Transfer Counter
DcDMAConfiguration
DMA Hardware
DMA Interrupt Reason
DMA Interrupt Enable
DMA Endpoint
DMA Burst Counter
DcInterrupt
DcChipID
Frame Number
DcScratch
Unlock Device
Interrupt Pulse Width
Test Mode
Peripheral controller-specific register overview
R/W
5
0
0
Rev. 05 — 13 March 2008
R/W
4
0
0
DEVADDR[6:0]
Reset value
00h
0000 0000h
0000h
00h
0000h
0000h
FFh
0000 0000h
0001h
04h
0000h
0000h
00h
0004h
0000 0000h
0015 8210h
0000h
0000h
0000h
001Eh
00h
R/W
3
0
0
…continued
R/W
Hi-Speed USB OTG controller
2
0
0
References
Section 10.6.2 on page 110
Section 10.6.3 on page 112
Section 10.6.4 on page 112
Section 10.6.5 on page 113
Section 10.6.6 on page 114
Section 10.6.7 on page 114
Section 10.7.1 on page 116
Section 10.7.2 on page 117
Section 10.7.3 on page 118
Section 10.7.4 on page 119
Section 10.7.5 on page 120
Section 10.7.6 on page 121
Section 10.7.7 on page 121
Section 10.7.8 on page 122
Section 10.8.1 on page 123
Section 10.8.2 on page 125
Section 10.8.3 on page 125
Section 10.8.4 on page 125
Section 10.8.5 on page 126
Section 10.8.6 on page 126
Section 10.8.7 on page 127
R/W
1
0
0
© NXP B.V. 2008. All rights reserved.
ISP1761
Table 98
104 of 163
R/W
0
0
0