ISP1761BE STEricsson, ISP1761BE Datasheet - Page 20

• Manufacturer Part Number: ISP1761BE
• Manufacturer: STEricsson

Specifications of ISP1761BE

• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: LQFP
• Rad Hardened: No
• Lead Free Status / Rohs Status: Supplier Unconfirmed

NXP Semiconductors
ISP1761_5
Product data sheet
Fig 6.
USB BUS
Memory segmentation and access block diagram
AND LOW-SPEED)
USB HIGH-SPEED
TRANSACTION
TRANSLATOR
(FULL-SPEED
7.3 Accessing the ISP1761 host controller memory: PIO and DMA
HOST AND
Both the CPU interface logic and the USB host controller require access to the internal
ISP1761 RAM at the same time. The internal arbiter controls these accesses to the
internal memory, organized internally on a 64-bit data bus width, allowing a maximum
bandwidth of 240 MB/s. This bandwidth avoids any bottleneck on accesses both from the
CPU interface and the internal USB host controller.
The CPU interface of the ISP1761 can be configured for a 16-bit or 32-bit data bus width.
When the ISP1761 is configured for a 16-bit data bus width, the upper unused 16 data
lines must be pulled up to V
together to a single 10 k pull-up resistor. The 16-bit or 32-bit data bus width
configuration is done by programming bit 8 of the HW Mode Control register. This will
determine the register and memory access types in both PIO and DMA modes to all
internal blocks: host controller, peripheral controller and OTG controller. All accesses must
be word-aligned for 16-bit mode and double-word aligned for 32-bit mode, where one
word = 16 bits. When accessing the host controller registers in 16-bit mode, the register
63 kB
address
data (64 bits)
control signals
PAYLOAD
PAYLOAD
ARBITER
PTD32
PTD32
PTD32
PTD1
PTD2
PTD1
PTD2
PTD1
PTD2
Rev. 05 — 13 March 2008
240 MB/s
CC(I/O)
ASYNC
PAYLOAD
ISOCHRONOUS
INTERRUPT
. This can be achieved by connecting DATA[31:16] lines
MEMORY MAPPED
INPUT/OUTPUT,
MANAGEMENT
CONTROLLER
INTERRUPT
REGISTERS
SLAVE DMA
CONTROL
MEMORY
UNIT,
AND
Hi-Speed USB OTG controller
D[15:0]/D[31:0]
DC_DREQ
HC_DREQ
HC_DACK
DC_DACK
DC_IRQ
HC_IRQ
A[17:1]
CS_N
RD_N
WR_N
© NXP B.V. 2008. All rights reserved.
ISP1761
PROCESSOR
MICRO-
004aaa568
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