ISP1761BE STEricsson, ISP1761BE Datasheet - Page 122

• Manufacturer Part Number: ISP1761BE
• Manufacturer: STEricsson

Specifications of ISP1761BE

• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: LQFP
• Rad Hardened: No
• Lead Free Status / Rohs Status: Supplier Unconfirmed

NXP Semiconductors
Table 136. DMA Interrupt Enable register (address 0254h) bit allocation
[1]
Table 137. DMA Endpoint register (address 0258h) bit allocation
ISP1761_5
Product data sheet
Bit
Symbol
Reset
Bus reset
Access
Bit
Symbol
Reset
Bus reset
Access
Bit
Symbol
The reserved bits should always be written with the reset value.
10.7.6 DMA Interrupt Enable register
10.7.7 DMA Endpoint register
R/W
R/W
15
0
0
7
0
0
7
Table 134. DMA Interrupt Reason register (address 0250h) bit description
Table 135. Internal EOT-functional relation with the DMA_XFER_OK bit
This 2 bytes register controls the interrupt generation of the source bits in the DMA
Interrupt Reason register. The bit allocation is given in
given in
Logic 1 enables the interrupt generation. The values after a (bus) reset are logic 0
(disabled).
This 1 byte register selects a USB endpoint FIFO as the source or destination for DMA
transfers. The bit allocation is given in
Bit
9
8
7 to 0
INT_EOT
1
1
0
reserved
R/W
R/W
14
0
0
6
0
0
6
Table
reserved
Symbol
-
DMA_XFER_OK
-
[1]
DMA_XFER_OK
0
1
1
134.
[1]
R/W
R/W
13
0
0
5
0
0
5
Rev. 05 — 13 March 2008
Description
reserved
DMA Transfer OK: Logic 1 indicates that the DMA transfer has
been completed, that is, DMA transfer counter has become zero.
reserved
IE_GDMA_
STOP
Description
During the DMA transfer, there is a premature termination with
short packet.
DMA transfer is completed with a short packet and the DMA
transfer counter has reached 0.
DMA transfer is completed without any short packet and the
DMA transfer counter has reached 0.
R/W
R/W
12
0
0
4
0
0
4
reserved
Table
reserved
[1]
R/W
R/W
137.
11
0
0
3
0
0
3
[1]
EPIDX[2:0]
IE_INT_
Table
EOT
R/W
R/W
10
0
0
2
0
0
2
Hi-Speed USB OTG controller
136. The bit description is
reserved
R/W
R/W
9
0
0
1
0
0
1
© NXP B.V. 2008. All rights reserved.
…continued
ISP1761
[1]
XFER_OK
IE_DMA_
DMADIR
121 of 163
R/W
R/W
8
0
0
0
0
0
0