STM8AF52AA STMicroelectronics, STM8AF52AA Datasheet - Page 24

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STM8AF52AA

Manufacturer Part Number
STM8AF52AA
Description
STM8AF52 CAN Line
Manufacturer
STMicroelectronics
Datasheet

Specifications of STM8AF52AA

Max Fcpu
24 MHz
Program Memory
32 to 128 Kbytes Flash program; data retention 20 years at 55 °C
Data Memory
up to 2 Kbytes true data EEPROM; endurance 300 kcycles
Ram
2 Kbytes to 6 Kbytes
Advanced Control Timer
16-bit, 4 CAPCOM channels, 3 complementary outputs, dead-time insertion and flexible synchronization
Product overview
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communication interface which supports extensive LIN functions tailored for LIN slave
applications. In LIN mode it is compliant to the LIN standards rev 1.2 to rev 2.1.
Detailed feature list:
LIN mode
Master mode
Slave mode
UART mode
LIN break and delimiter generation
LIN break and delimiter detection with separate flag and interrupt source for read back
checking.
Autonomous header handling – one single interrupt per valid header
Mute mode to filter responses
Identifier parity error checking
LIN automatic resynchronization, allowing operation with internal RC oscillator (HSI)
clock source
Break detection at any time, even during a byte reception
Header errors detection:
Full duplex, asynchronous communications - NRZ standard format (mark/space)
High-precision baud rate generator
Programmable data word length (8 or 9 bits) – 1 or 2 stop bits – parity control
Separate enable bits for transmitter and receiver
Error detection flags
Reduced power consumption mode
Multi-processor communication - enter mute mode if address match does not occur
Wakeup from mute mode (by idle line detection or address mark detection)
Two receiver wakeup modes:
Delimiter too short
Synch field error
Deviation error (if automatic resynchronization is enabled)
Framing error in synch field or identifier field
Header time-out
A common programmable transmit and receive baud rates up to f
Address bit (MSB)
Idle line
Doc ID 14395 Rev 8
STM8AF52/62xx, STM8AF51/61xx
MASTER
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