STM8AF52AA

Manufacturer Part NumberSTM8AF52AA
DescriptionSTM8AF52 CAN Line
ManufacturerSTMicroelectronics
STM8AF52AA datasheet
 


Specifications of STM8AF52AA

Max Fcpu24 MHzProgram Memory32 to 128 Kbytes Flash program; data retention 20 years at 55 °C
Data Memoryup to 2 Kbytes true data EEPROM; endurance 300 kcyclesRam2 Kbytes to 6 Kbytes
Advanced Control Timer16-bit, 4 CAPCOM channels, 3 complementary outputs, dead-time insertion and flexible synchronization  
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Page 82/106

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Electrical characteristics
2
10.3.10
I
C interface characteristics
2
Table 43.
I
C characteristics
Symbol
t
SCL clock low time
w(SCLL)
t
SCL clock high time
w(SCLH)
t
SDA setup time
su(SDA)
t
SDA data hold time
h(SDA)
t
SDA and SCL rise time
r(SDA)
t
(V
3 V to 5.5 V)
r(SCL)
DD
t
SDA and SCL fall time
f(SDA)
t
(V
3 V to 5.5 V)
f(SCL)
DD
t
START condition hold time
h(STA)
t
Repeated START condition setup time
su(STA)
t
STOP condition setup time
su(STO)
STOP to START condition time
t
w(STO:STA)
(bus free)
C
Capacitive load for each bus line
b
1. f
, must be at least 8 MHz to achieve max fast I
MASTER
2. Data based on standard I
3. The maximum hold time of the start condition has only to be met if the interface does not stretch the low
time
4. The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the
undefined region of the falling edge of SCL
82/106
Standard mode I
Parameter
Min
4.7
4.0
250
(3)
0
4.0
4.7
4.0
4.7
2
C speed (400 kHz)
2
C protocol requirement, not tested in production
Doc ID 14395 Rev 8
STM8AF52/62xx, STM8AF51/61xx
2
2
(1)
C Fast mode I
C
(2)
(2)
(2)
(2)
Max
Min
Max
1.3
0.6
100
(4)
(3)
0
900
1000
300
300
300
0.6
0.6
0.6
1.3
400
400
Unit
µs
ns
µs
µs
µs
pF