ep2s130 Altera Corporation, ep2s130 Datasheet - Page 112

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ep2s130

Manufacturer Part Number
ep2s130
Description
Stratix Ii Device Family Data Sheet
Manufacturer
Altera Corporation
Datasheet

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Document Revision History
Document
Revision History
2–104
Stratix II Device Handbook, Volume 1
May 2007, v4.3 Updated
August 2006,
v4.2
April 2006,
v4.1
December
2005, v4.0
July 2005, v3.1
May 2005, v3.0
March 2005,
2.1
Table 2–27. Document Revision History (Part 1 of 2)
Document
Date and
Version
Updated note in the
Deleted Tables 2-11 and 2-12.
Updated notes to:
Updated notes to
Moved Document Revision History to end of the chapter.
Updated Table 2–18 with note.
Updated “Clock Control Block” section.
Figure 2–41
Figure 2–42
Figure 2–43
Figure 2–45
Updated Table 2–13.
Removed Note 2 from Table 2–16.
Updated “On-Chip Termination” section and Table 2–19 to
include parallel termination with calibration information.
Added new “On-Chip Parallel Termination with Calibration”
section.
Updated Figure 2–44.
Updated HyperTransport technology information in Table 2–18.
Updated HyperTransport technology information in
Figure 2–57.
Added information on the asynchronous clear signal.
Updated “Functional Description” section.
Updated Table 2–3.
Updated “Clock Control Block” section.
Updated Tables 2–17 through 2–19.
Updated Tables 2–20 through 2–22.
Updated Figure 2–57.
Updated “Functional Description” section.
Updated Table 2–3.
“Clock Control Block”
Table 2–27
Table
“Clock Control Block”
2–18.
shows the revision history for this chapter.
Changes Made
section.
section.
Summary of Changes
Added parallel on-
chip termination
description and
specification.
Changed RCLK
names to match the
Quartus II software in
Table 2–13.
Altera Corporation
May 2007

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