ep2s130 Altera Corporation, ep2s130 Datasheet - Page 222

• Manufacturer Part Number: ep2s130
• Description: Stratix Ii Device Family Data Sheet
• Manufacturer: Altera Corporation

Duty Cycle Distortion
5–86
Stratix II Device Handbook, Volume 1
Note to
(1)
Note to
(1)
(2)
LVDS/ HyperTransport
technology
3.3-V LVTTL
3.3-V LVCMOS
2.5V
1.8V
1.5-V LVCMOS
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
SSTL-18 Class II
1.8-V HSTL Class I
1.8-V HSTL Class II
1.5-V HSTL Class I
1.5-V HSTL Class II
1.2-V HSTL
LVPECL
Column DDIO Output I/O
Table 5–86. Maximum DCD for DDIO Output on Row I/O Pins with PLL in the
Clock Path (Part 2 of 2)
Table 5–87. Maximum DCD for DDIO Output on Column I/O with PLL in the
Clock Path
Row DDIO Output I/O
The DCD specification is based on a no logic array noise condition.
The DCD specification is based on a no logic array noise condition.
1.2-V HSTL is only supported in -3 devices.
Table
Table
Standard
Standard
5–86:
5–87:
Note (1)
Maximum DCD (PLL Output Clock Feeding
Maximum DCD (PLL Output Clock Feeding
Note (1)
-3 Device
-3 Device
145
100
140
155
180
180
85
85
65
60
50
70
60
60
55
85
DDIO Clock Port)
DDIO Clock Port)
-4 & -5 Device
-4 & -5 Device
160
110
100
155
100
180
95
75
70
65
80
70
70
70
180
Altera Corporation
-
May 2007
Unit
Unit
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ps
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ps
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ps
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ps
ps
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ps