ep2s130 Altera Corporation, ep2s130 Datasheet - Page 215

• Manufacturer Part Number: ep2s130
• Description: Stratix Ii Device Family Data Sheet
• Manufacturer: Altera Corporation

Figure 5–9. DCD Measurement Technique for DDIO (Double-Data Rate) Outputs
Altera Corporation
May 2007
clk
INPUT
VCC
However, when the output is a double data rate input/output (DDIO)
signal, both edges of the input clock signal (positive and negative) trigger
output transitions
clock and the input clock buffer affect the output DCD.
When an FPGA PLL generates the internal clock, the PLL output clocks
the IOE block. As the PLL only monitors the positive edge of the reference
clock input and internally re-creates the output clock signal, any DCD
present on the reference clock is filtered out. Therefore, the DCD for a
DDIO output with PLL in the clock path is better than the DCD for a
DDIO output without PLL in the clock path.
Tables 5–80
derivation for different I/O standards on Stratix II devices. Examples are
also provided that show how to calculate DCD as a percentage.
IOE
3.3-V LVTTTL
3.3-V LVCMOS
2.5 V
Table 5–80. Maximum DCD for Non-DDIO Output on Row I/O Pins (Part 1
of 2)
Row I/O Output
Standard
NOT
inst8
Note (1)
through
GND
V
CC
(Figure
DFF
inst2
DFF
inst3
5–87
D
D
CLRN
CLRN
PRN
PRN
-3 Devices
give the maximum DCD in absolution
5–9). Therefore, any distortion on the input
Q
Q
245
125
105
Maximum DCD for Non-DDIO Output
Stratix II Device Handbook, Volume 1
-4 & -5 Devices
DC & Switching Characteristics
275
155
135
OUTPUT
output
Unit
ps
ps
ps
5–79