ep2s130 Altera Corporation, ep2s130 Datasheet - Page 70

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ep2s130

Manufacturer Part Number
ep2s130
Description
Stratix Ii Device Family Data Sheet
Manufacturer
Altera Corporation
Datasheet

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PLLs & Clock Networks
2–62
Stratix II Device Handbook, Volume 1
Figure 2–42. Global & Regional Clock Connections from Corner Clock Pins &
Fast PLL Outputs
Note to
(1)
The corner fast PLLs can also be driven through the global or regional clock
networks. The global or regional clock input can be driven by an output from
another PLL, a pin-driven dedicated global or regional clock, or through a clock
control block, provided the clock control block is fed by an output from another
PLL or a pin-driven dedicated global or regional clock. An internally generated
global signal cannot drive the PLL.
Figure
2–42:
Note (1)
Altera Corporation
May 2007

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