ep2s130 Altera Corporation, ep2s130 Datasheet - Page 93

• Manufacturer Part Number: ep2s130
• Description: Stratix Ii Device Family Data Sheet
• Manufacturer: Altera Corporation

Altera Corporation
May 2007
The bus-hold circuitry also pulls undriven pins away from the input
threshold voltage where noise can cause unintended high-frequency
switching. You can select this feature individually for each I/O pin. The
bus-hold output drives no higher than V
signals. If the bus-hold feature is enabled, the programmable pull-up
option cannot be used. Disable the bus-hold feature when the I/O pin has
been configured for differential signals.
The bus-hold circuitry uses a resistor with a nominal resistance (R
approximately 7 kΩ to weakly pull the signal level to the last-driven state.
See the DC & Switching Characteristics chapter in the Stratix II Device
Handbook, Volume 1, for the specific sustaining current driven through this
resistor and overdrive current used to identify the next-driven input
level. This information is provided for each V
The bus-hold circuitry is active only after configuration. When going into
user mode, the bus-hold circuit captures the value on the pin present at
the end of configuration.
Programmable Pull-Up Resistor
Each Stratix II device I/O pin provides an optional programmable
pull-up resistor during user mode. If you enable this feature for an I/O
pin, the pull-up resistor (typically 25 kΩ) weakly holds the output to the
V
Programmable pull-up resistors are only supported on user I/O pins, and
are not supported on dedicated configuration pins, JTAG pins or
dedicated clock pins.
Advanced I/O Standard Support
Stratix II device IOEs support the following I/O standards:
■
■
■
■
■
■
■
■
■
■
■
■
■
CCIO
3.3-V LVTTL/LVCMOS
2.5-V LVTTL/LVCMOS
1.8-V LVTTL/LVCMOS
1.5-V LVCMOS
3.3-V PCI
3.3-V PCI-X mode 1
LVDS
LVPECL (on input and output clocks only)
HyperTransport technology
Differential 1.5-V HSTL Class I and II
Differential 1.8-V HSTL Class I and II
Differential SSTL-18 Class I and II
Differential SSTL-2 Class I and II
level of the output pin’s bank.
Stratix II Device Handbook, Volume 1
CCIO
to prevent overdriving
CCIO
voltage level.
Stratix II Architecture
BH
2–85
) of