ep2s130 Altera Corporation, ep2s130 Datasheet - Page 77

• Manufacturer Part Number: ep2s130
• Description: Stratix Ii Device Family Data Sheet
• Manufacturer: Altera Corporation

Figure 2–45. Stratix II Device Fast PLL
Notes to
(1)
(2)
(3)
(4)
(5)
I/O Structure
Altera Corporation
May 2007
Clock
Input
The global or regional clock input can be driven by an output from another PLL, a pin-driven dedicated global or
regional clock, or through a clock control block, provided the clock control block is fed by an output from another
PLL or a pin-driven dedicated global or regional clock. An internally generated global signal cannot drive the PLL.
In high-speed differential I/O support mode, this high-speed PLL clock feeds the SERDES circuitry. Stratix II
devices only support one rate of data transfer per fast PLL in high-speed differential I/O support mode.
This signal is a differential I/O SERDES control signal.
Stratix II fast PLLs only support manual clock switchover.
If the design enables this ÷2 counter, then the device can use a VCO frequency range of 150 to 520 MHz.
Figure
Global or
regional clock (1)
Global or
regional clock (1)
4
2–45:
f
Shaded Portions of the
PLL are Reconfigurable
Circuitry (4)
Switchover
Clock
Fast PLLs
Stratix II devices contain up to eight fast PLLs with high-speed serial
interfacing ability.
See the PLLs in Stratix II & Stratix II GX Devices chapter in volume 2 of
the Stratix II Device Handbook or the Stratix II GX Device Handbook for
more information on enhanced and fast PLLs. See
Differential I/O with DPA Support” on page 2–96
on high-speed differential I/O support.
The Stratix II IOEs provide many features, including:
■
■
■
■
■
■
■
■
÷n
Dedicated differential and single-ended I/O buffers
3.3-V, 64-bit, 66-MHz PCI compliance
3.3-V, 64-bit, 133-MHz PCI-X 1.0 compliance
Joint Test Action Group (JTAG) boundary-scan test (BST) support
On-chip driver series termination
On-chip parallel termination
On-chip termination for differential standards
Programmable pull-up during configuration
Frequency
Detector
Phase
PFD
Notes
Charge
(1), (2),
Pump
Figure 2–45
Filter
Loop
(3)
÷m
shows a diagram of the fast PLL.
VCO
VCO Phase Selection
Selectable at each PLL
Output Port
Stratix II Device Handbook, Volume 1
÷k
(5)
8
Post-Scale
“High-Speed
for more information
Counters
÷c0
÷c1
÷c2
÷c3
Stratix II Architecture
4
4
8
8
2–69
diffioclk0
load_en0
load_en1
diffioclk1
Global clocks
Regional clocks
to DPA block
(2)
(3)
(3)
(2)