ep2s130 Altera Corporation, ep2s130 Datasheet - Page 172

• Manufacturer Part Number: ep2s130
• Description: Stratix Ii Device Family Data Sheet
• Manufacturer: Altera Corporation

Timing Model
5–36
Stratix II Device Handbook, Volume 1
t
t
t
t
t
t
t
t
t
t
t
t
S U
H
C O
I N R E G 2 P I P E 9
I N R E G 2 P I P E 1 8
I N R E G 2 P I P E 3 6
P I P E 2 O U T R E G 2 A D D
P I P E 2 O U T R E G 4 A D D
P D 9
P D 1 8
P D 3 6
C L R
Table 5–39. DSP Block Internal Timing Microparameters (Part 1 of 2)
Symbol
Input, pipeline, and
output register setup
time before clock
Input, pipeline, and
output register hold
time after clock
Input, pipeline, and
output register clock-
to-output delay
Input register to DSP
block pipeline register
in 9 × 9-bit mode
Input register to DSP
block pipeline register
in 18 × 18-bit mode
Input register to DSP
block pipeline register
in 36 × 36-bit mode
DSP block pipeline
register to output
register delay in two-
multipliers adder
mode
DSP block pipeline
register to output
register delay in four-
multipliers adder
mode
Combinational input
to output delay for
9 × 9
Combinational input
to output delay for
18 × 18
Combinational input
to output delay for
36 × 36
Minimum clear pulse
width
Parameter
1,312 2,030 1,312 2,030 1,250
1,302 2,010 1,302 2,110 1,240
1,302 2,010 1,302 2,110 1,240
1,134 1,850 1,134 1,942 1,080
2,100 2,880 2,100 3,024 2,000
2,110 2,990 2,110 3,139 2,010
2,939 4,450 2,939 4,672 2,800
2,212
Min
180
924
(3)
50
Grade
-3 Speed
0
1,450
Max
(1)
0
2,322
Min
189
924
(3)
52
Grade
-3 Speed
0
1,522
Max
(2)
0
1,312
1,302
1,302
1,134
2,100
2,110
2,939
2,543
2,543
Min
206
206
880
924
(4)
57
57
-4 Speed
0
0
Grade
2,334 1,312 2,720
2,311 1,302 2,693
2,311 1,302 2,693
1,667
2,127 1,134 2,479
3,312 2,100 3,859
3,438 2,110 4,006
5,117 2,939 5,962
Max
0
Altera Corporation
2,964
Min
241
924
(3)
67
-5 Speed
0
Grade
1,943
Max
May 2007
0
Unit
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps