ep2s130 Altera Corporation, ep2s130 Datasheet - Page 232

• Manufacturer Part Number: ep2s130
• Description: Stratix Ii Device Family Data Sheet
• Manufacturer: Altera Corporation

JTAG Timing Specifications
JTAG Timing
Specifications
Figure 5–10. Stratix II JTAG Waveforms
5–96
Stratix II Device Handbook, Volume 1
TMS
TDO
TCK
TDI
t
JCH
t
Figure 5–10
JPZX
Notes to
(1)
(2)
(3)
Notes to
(1)
(2)
t
O U T H A L F J I T T E R
Table 5–100. DQS Phase Offset Delay Per Stage
Table 5–101. DDIO Outputs Half-Period Jitter
t
JCP
The delay settings are linear.
The valid settings for phase offset are -64 to +63 for frequency mode 0 and -32 to
+31 for frequency modes 1, 2, and 3.
The typical value equals the average of the minimum and maximum values.
The worst-case half period is equal to the ideal half period subtracted by the DCD
and half-period jitter values.
The half-period jitter was characterized using a PLL driving DDIO outputs.
Name
t
JCL
Speed Grade
Table
Table
shows the timing requirements for the JTAG signals.
-3
-4
-5
5–100:
5–101:
t
Half-period jitter (PLL driving DDIO outputs)
JPCO
t
JPSU
Description
Min
9
9
9
t
JPH
t
JPXZ
Notes
Max
14
14
15
Notes
(1),
Altera Corporation
(1), (2),
(2)
Max
200
(3)
Unit
May 2007
ps
ps
ps
Unit
ps