ep2s130 Altera Corporation, ep2s130 Datasheet - Page 188

• Manufacturer Part Number: ep2s130
• Description: Stratix Ii Device Family Data Sheet
• Manufacturer: Altera Corporation

Timing Model
5–52
Stratix II Device Handbook, Volume 1
Notes to
(1)
(2)
(3)
Input delay from
pin to internal
cells
Input delay from
pin to input
register
Delay from
output register
to output pin
Output enable
pin delay
Table 5–70. Stratix II IOE Programmable Delay on Row Pins
Parameter
The incremental values for the settings are generally linear. For the exact delay associated with each setting, use the
latest version of the Quartus II software.
The first number is the minimum timing parameter for industrial devices. The second number is the minimum
timing parameter for commercial devices.
The first number applies to -3 speed grade EP2S15, EP2S30, EP2S60, and EP2S90 devices. The second number
applies to -3 speed grade EP2S130 and EP2S180 devices.
Table
5–70:
Pad to I/O
dataout to logic
array
Pad to I/O input
register
I/O output
register to pad
t
Paths Affected
X Z
, t
Z X
Default Capacitive Loading of Different I/O Standards
See
LVTTL
LVCMOS
2.5 V
1.8 V
1.5 V
PCI
PCI-X
SSTL-2 Class I
Table 5–71. Default Loading of Different I/O Standards for Stratix II (Part 1
of 2)
Table 5–71
Available
Settings
64
8
2
2
for default capacitive loading of different I/O standards.
Offset
(ps)
Min
Timing
Minimum
0
0
0
0
0
0
0
0
I/O Standard
Offset
1,697
1,782
1,956
2,054
Max
(ps)
316
332
305
320
(2)
Offset
Min
(ps)
Grade
0
0
0
0
0
0
0
0
-3 Speed
Note (1)
Offset
2,876
3,020
3,270
3,434
Max
(3)
(ps)
525
525
507
507
Offset
Min
(ps)
0
0
0
0
-4 Speed
Grade
Capacitive Load
Offset
3,308
3,761
Max
(ps)
575
556
Altera Corporation
10
10
0
0
0
0
0
0
Offset
Min
(ps)
0
0
0
0
-5 Speed
Grade
May 2007
Offset
3,853
4,381
Unit
Max
(ps)
670
647
pF
pF
pF
pF
pF
pF
pF
pF