ep2s130 Altera Corporation, ep2s130 Datasheet - Page 123

• Manufacturer Part Number: ep2s130
• Description: Stratix Ii Device Family Data Sheet
• Manufacturer: Altera Corporation

Altera Corporation
May 2007
1
Device Configuration Data Decompression
Stratix II FPGAs support decompression of configuration data, which
saves configuration memory space and time. This feature allows you to
store compressed configuration data in configuration devices or other
memory, and transmit this compressed bit stream to Stratix II FPGAs.
During configuration, the Stratix II FPGA decompresses the bit stream in
real time and programs its SRAM cells.
Stratix II FPGAs support decompression in the FPP (when using a
MAX II device/microprocessor and flash memory), AS and PS
configuration schemes. Decompression is not supported in the PPA
configuration scheme nor in JTAG-based configuration.
Remote System Upgrades
Shortened design cycles, evolving standards, and system deployments in
remote locations are difficult challenges faced by modern system
designers. Stratix II devices can help effectively deal with these
challenges with their inherent re-programmability and dedicated
circuitry to perform remote system updates. Remote system updates help
deliver feature enhancements and bug fixes without costly recalls, reduce
time to market, and extend product life.
Stratix II FPGAs feature dedicated remote system upgrade circuitry to
facilitate remote system updates. Soft logic (Nios
implemented in the Stratix II device can download a new configuration
image from a remote location, store it in configuration memory, and direct
the dedicated remote system upgrade circuitry to initiate a
reconfiguration cycle. The dedicated circuitry performs error detection
during and after the configuration process, recovers from any error
condition by reverting back to a safe configuration image, and provides
An encryption configuration file is the same size as a non-
encryption configuration file. When using a serial configuration
scheme such as passive serial (PS) or active serial (AS),
configuration time is the same whether or not the design
security feature is enabled. If the fast passive parallel (FPP)
scheme us used with the design security or decompression
feature, a 4× DCLK is required. This results in a slower
configuration time when compared to the configuration time of
an FPGA that has neither the design security, nor
decompression feature enabled. For more information about
this feature, refer to AN 341: Using the Design Security Feature in
Stratix II Devices. Contact your local Altera sales representative
to request this document.
Stratix II Device Handbook, Volume 1
®
processor or user logic)
Configuration & Testing
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