ep2s130 Altera Corporation, ep2s130 Datasheet - Page 225

• Manufacturer Part Number: ep2s130
• Description: Stratix Ii Device Family Data Sheet
• Manufacturer: Altera Corporation

Altera Corporation
May 2007
Notes to
(1)
(2)
(3)
(4)
f
f
f
f
TCCS
SW
Output jitter
Output t
Output t
t
DPA run length
DPA jitter tolerance
DPA lock time
H S C L K
H S C L K
H S D R
H S D R D PA
DUTY
Table 5–90. High-Speed I/O Specifications for -4 Speed Grade
When J = 4 to 10, the SERDES block is used.
When J = 1 or 2, the SERDES block is bypassed.
The input clock frequency and the W factor must satisfy the following fast PLL VCO specification: 150 ≤ input clock
frequency × W ≤ 1,040.
The minimum specification is dependent on the clock source (fast PLL, enhanced PLL, clock pin, and so on) and
the clock routing resource (global, regional, or local) utilized. The I/O differential buffer and input register do not
have a minimum toggle rate.
(data rate)
(clock frequency)
= f
R I S E
FA L L
Table
Symbol
H S D R
(DPA data rate) J = 4 to 10 (LVDS, HyperTransport technology)
5–90:
/ W
W = 2 to 32 (LVDS, HyperTransport technology)
(3)
W = 1 (SERDES bypass, LVDS only)
W = 1 (SERDES used, LVDS only)
J = 4 to 10 (LVDS, HyperTransport technology)
J = 2 (LVDS, HyperTransport technology)
J = 1 (LVDS only)
All differential standards
All differential standards
All differential I/O standards
All differential I/O standards
Data channel peak-to-peak jitter
Parallel Rapid I/O
Table 5–90
grade Stratix II devices.
Miscellaneous
Standard
SPI-4
shows the high-speed I/O timing specifications for -4 speed
Conditions
0000000000
1111111111
00001111
10010000
10101010
01010101
Training
Pattern
Transition
Density
100%
10%
25%
50%
Notes
Stratix II Device Handbook, Volume 1
(1),
DC & Switching Characteristics
0.44
Min
150
150
256
256
256
150
330
256
256
16
16
(4)
(4)
45
-4 Speed Grade
-
(2)
Typ
50
1,040
1,040
6,400
Max
520
500
717
760
500
200
190
160
180
55
-
Number of
repetitions
Mbps
Mbps
Mbps
Mbps
MHz
MHz
MHz
Unit
ps
ps
ps
ps
ps
UI
UI
%
5–89