S9S12XS256J0CAL Freescale Semiconductor, S9S12XS256J0CAL Datasheet - Page 119

• Manufacturer Part Number: S9S12XS256J0CAL
• Description: MCU 256K FLASH 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S9S12XS256J0CAL

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 8K x 8
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Processor Series: S12XS
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 12 KB
• Interface Type: CAN, SCI, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 12
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: DEMO9S12XSFAME, EVB9S12XEP100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1
1
2.3.71
2.3.72
Freescale Semiconductor
RDR1AD0
PER0AD0
Address 0x0275
Address 0x0276
Read: Anytime.
Write: Anytime.
Read: Anytime.
Write: Anytime.
Field
Field
Reset
Reset
7-0
7-0
W
W
R
R
RDR1AD07
PER0AD07
Port AD0 reduced drive—Select reduced drive for output pin
This bit configures the drive strength of the associated output pin as either full or reduced. If a pin is used as input
this bit has no effect. The reduced drive function is independent of which function is being used on a particular pin.
1 Reduced drive selected (approx. 1/5 of the full drive strength)
0 Full drive strength enabled
Port AD0 pull device enable—Enable pull-up device on input pin
This bit controls whether a pull device on the associated port input pin is active. If a pin is used as output this bit has
no effect. The polarity is selected by the related polarity select register bit.
1 Pull device enabled
0 Pull device disabled
Port AD0 Reduced Drive Register 1 (RDR1AD0)
Port AD0 Pull Up Enable Register 0 (PER0AD0)
0
0
7
7
RDR1AD06
PER0AD06
Figure 2-69. Port AD0 Reduced Drive Register 1 (RDR1AD0)
Figure 2-70. Port AD0 Pull Device Up Register 0 (PER0AD0)
0
0
6
6
Table 2-68. RDR1AD0 Register Field Descriptions
Table 2-69. PER0AD0 Register Field Descriptions
RDR1AD05
PER0AD05
S12XS Family Reference Manual, Rev. 1.11
0
0
5
5
RDR1AD04
PER0AD04
0
0
4
4
Description
Description
RDR1AD03
PER0AD03
3
0
3
0
RDR1AD02
PER0AD02
0
0
Port Integration Module (S12XSPIMV1)
2
2
RDR1AD01
PER0AD01
Access: User read/write
Access: User read/write
0
0
1
1
RDR1AD00
PER0AD00
0
0
0
0
119
1
1