S9S12XS256J0CAL Freescale Semiconductor, S9S12XS256J0CAL Datasheet - Page 59

• Manufacturer Part Number: S9S12XS256J0CAL
• Description: MCU 256K FLASH 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S9S12XS256J0CAL

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 8K x 8
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Processor Series: S12XS
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 12 KB
• Interface Type: CAN, SCI, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 12
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: DEMO9S12XSFAME, EVB9S12XEP100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 2
Port Integration Module (S12XSPIMV1)
Revision History
2.1
2.1.1
The S12XS family Port Integration Module establishes the interface between the peripheral modules and
the I/O pins for all ports. It controls the electrical pin properties as well as the signal prioritization and
multiplexing on shared pins.
This document covers:
Most I/O pins can be configured by register bits to select data direction and drive strength, to enable and
select pull-up or pull-down devices.
Freescale Semiconductor
Revision
Number
V01.04
V01.05
V01.06
•
•
•
•
•
•
•
•
Port A, B and K used as general purpose I/O
Port E associated with the IRQ, XIRQ interrupt inputs
Port T associated with 1 timer module
Port S associated with 2 SCI module and 1 SPI module
Port M associated with 1 MSCAN
Port P connected to the PWM - inputs can be used as an external interrupt source
Port H and J used as general purpose I/O - inputs can be used as an external interrupt source
Port AD associated with one 16-channel ATD module
Introduction
Revision Date
Overview
18 Dec 2009
31 Mar 2009
02 Apr 2008
Table 2-1./2-61
Sections
Affected
S12XS Family Reference Manual, Rev. 1.11
• Corrected reduced drive strength to 1/5
• Separated PE1,0 bit descriptions from other PE GPIO
• Corrected PERJ bit description
• Orthographical corrections
• Corrected PP0, PM0 pin descriptions
• Added function independency to wired-or bit descriptions
• Minor corrections
Description of Changes
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