S9S12XS256J0CAL Freescale Semiconductor, S9S12XS256J0CAL Datasheet - Page 492

• Manufacturer Part Number: S9S12XS256J0CAL
• Description: MCU 256K FLASH 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S9S12XS256J0CAL

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 8K x 8
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Processor Series: S12XS
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 12 KB
• Interface Type: CAN, SCI, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 12
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: DEMO9S12XSFAME, EVB9S12XEP100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Voltage Regulator (S12VREGL3V3V1)
17.2
Due to the nature of VREG_3V3 being a voltage regulator providing the chip internal power supply
voltages, most signals are power supply signals connected to pads.
17.2.1
Signal VDDR is the power input of VREG_3V3. All currents sourced into the regulator loads flow through
this pin. A chip external decoupling capacitor (100 nF...220 nF, X7R ceramic) between VDDR and VSSR
(if VSSR is not available VSS) can smooth ripple on VDDR.
For entering Shutdown Mode, pin VDDR should also be tied to ground on devices without VREGEN pin.
17.2.2
Signals VDDA/VSSA
regulator. Internal precision reference circuits are supplied from these signals. A chip external decoupling
capacitor (100 nF...220 nF, X7R ceramic) between VDDA and VSSA can further improve the quality of
this supply.
17.2.3
Signals VDD/VSS are the primary outputs of VREG_3V3 that provide the power supply for the core logic.
These signals are connected to device pins to allow external decoupling capacitors (220 nF, X7R ceramic).
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Table 17-2
External Signal Description
shows all signals of VREG_3V3 associated with pins.
VDDR — Regulator Power Input Pins
VDDA, VSSA — Regulator Reference Supply Pins
VDD, VSS — Regulator Output1 (Core Logic) Pins
Check device level specification for connectivity of the signals.
VREGEN (optional)
VREG_API
(optional)
VDDPLL
VSSPLL
VDDR
VDDX
Name
VDDA
VSSA
VDDF
,
VDD
VSS
which are supposed to be relatively quiet, are used to supply the analog parts of the
S12XS Family Reference Manual, Rev. 1.11
Power input (positive supply)
Quiet input (positive supply)
Quiet input (ground)
Power input (positive supply)
Primary output (positive supply)
Primary output (ground)
Secondary output (positive supply)
Tertiary output (positive supply)
Tertiary output (ground)
Optional Regulator Enable
VREG Autonomous Periodical
Interrupt output
Table 17-2. Signal Properties
Function
NOTE
Reset State
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Freescale Semiconductor
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