S9S12XS256J0CAL Freescale Semiconductor, S9S12XS256J0CAL Datasheet - Page 688

• Manufacturer Part Number: S9S12XS256J0CAL
• Description: MCU 256K FLASH 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S9S12XS256J0CAL

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 8K x 8
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Processor Series: S12XS
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 12 KB
• Interface Type: CAN, SCI, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 12
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: DEMO9S12XSFAME, EVB9S12XEP100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Electrical Characteristics
A.6
This section summarizes the electrical characteristics of the various startup scenarios for oscillator and
phase-locked loop (PLL).
A.6.1
Table A-22
startup behavior can be found in the Clock and Reset Generator (CRG) block description
1
A.6.1.1
The release level V
if the device is powered externally. After releasing the POR reset the oscillator and the clock quality check
are started. If after a time t
clock. The fastest startup time possible is given by n
A.6.1.2
Provided an appropriate external reset signal is applied to the MCU, preventing the CPU from executing
code when V
the PORF bit in the CRG flags register has not been set.
A.6.1.3
When external reset is asserted for a time greater than PW
reset, and the CPU starts fetching the reset vector without doing a clock quality check, if there was an
oscillation before reset.
A.6.1.4
Out of stop the controller can be woken up by an external interrupt. A clock quality check as after POR is
performed before releasing the clocks to the system.
If the MCU is woken-up by an interrupt and the fast wake-up feature is enabled (FSTWKP = 1 and
SCME = 1), the system will resume operation in self-clock mode after t
688
Conditions are shown in
Num C
Including voltage regulator startup; V
1
2
3
4
D Reset input pulse width, minimum input time
D Startup from reset
D Wait recovery startup time
D Fast wakeup from STOP
Reset, Oscillator and PLL
summarizes several startup characteristics explained in this section. Detailed description of the
Startup
DD35
POR
SRAM Data Retention
External Reset
Stop Recovery
is out of specification limits, the SRAM contents integrity is guaranteed if after the reset
PORR
Table
and the assert level V
CQOUT
A-4unless otherwise noted
1
Rating
DD
no valid oscillation is detected, the MCU will start using the internal self
S12XS Family Reference Manual, Rev. 1.11
Table A-22. Startup Characteristics
/V
DDF
filter capacitors 220 nF, V
PORA
are derived from the V
uposc
.
RSTL
Symbol
PW
n
t
WRS
t
RST
fws
DD35
RSTL
the CRG module generates an internal
= 5 V, T= 25°C
Min
192
—
—
fws
2
DD
.
supply. They are also valid
Typ
50
—
—
—
Freescale Semiconductor
Max
196
100
14
—
Unit
n
t
t
µs
osc
cyc
osc