S9S12XS256J0CAL Freescale Semiconductor, S9S12XS256J0CAL Datasheet - Page 175

• Manufacturer Part Number: S9S12XS256J0CAL
• Description: MCU 256K FLASH 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S9S12XS256J0CAL

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 8K x 8
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Processor Series: S12XS
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 12 KB
• Interface Type: CAN, SCI, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 12
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: DEMO9S12XSFAME, EVB9S12XEP100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

5.3.2.4
Register Global Address 0x7FFF08
Read: All modes through BDM operation when not secured
Write: All modes through BDM operation when not secured
5.3.3
The family ID is a 8-bit value located in the firmware ROM (at global address: 0x7FFF0F). The read-only
value is a unique family ID which is 0xC1 for S12X devices.
5.4
The BDM receives and executes commands from a host via a single wire serial interface. There are two
types of BDM commands: hardware and firmware commands.
Hardware commands are used to read and write target system memory locations and to enter active
background debug mode, see
includes all memory that is accessible by the CPU.
Firmware commands are used to read and write CPU resources and to exit from active background debug
mode, see
accumulator (D), X index register (X), Y index register (Y), stack pointer (SP), and program counter (PC).
Hardware commands can be executed at any time and in any mode excluding a few exceptions as
highlighted (see
“Security”). Firmware commands can only be executed when the system is not secure and is in active
background debug mode (BDM).
Freescale Semiconductor
BGP[6:0]
Reset
BGAE
Field
6–0
7
W
R
Functional Description
Section 5.4.4, “Standard BDM Firmware
BGAE
Family ID Assignment
BDM Global Page Access Enable Bit — BGAE enables global page access for BDM hardware and firmware
read/write instructions The BDM hardware commands used to access the BDM registers (READ_BD_ and
WRITE_BD_) can not be used for global accesses even if the BGAE bit is set.
0 BDM Global Access disabled
1 BDM Global Access enabled
BDM Global Page Index Bits 6–0 — These bits define the extended address bits from 22 to 16. For more
detailed information regarding the global page window scheme, please refer to the S12X_MMC Block Guide.
BDM Global Page Index Register (BDMGPR)
7
0
Section 5.4.3, “BDM Hardware
BGP6
6
0
Figure 5-6. BDM Global Page Register (BDMGPR)
Section 5.4.3, “BDM Hardware
Table 5-5. BDMGPR Field Descriptions
S12XS Family Reference Manual, Rev. 1.11
BGP5
5
0
BGP4
Commands”) and in secure mode (see
4
0
Commands”. The CPU resources referred to are the
Description
BGP3
Commands”. Target system memory
3
0
Background Debug Module (S12XBDMV2)
BGP2
2
0
BGP1
1
0
Section 5.4.1,
BGP0
0
0
175