S9S12XS256J0CAL Freescale Semiconductor, S9S12XS256J0CAL Datasheet - Page 193

• Manufacturer Part Number: S9S12XS256J0CAL
• Description: MCU 256K FLASH 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S9S12XS256J0CAL

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 8K x 8
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Processor Series: S12XS
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 12 KB
• Interface Type: CAN, SCI, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 12
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: DEMO9S12XSFAME, EVB9S12XEP100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 6
S12X Debug (S12XDBGV3) Module
6.1
The S12XDBG module provides an on-chip trace buffer with flexible triggering capability to allow non-
intrusive debug of application software. The S12XDBG module is optimized for the S12X 16-bit
architecture and allows debugging of CPU12X module operations.
Typically the S12XDBG module is used in conjunction with the S12XBDM module, whereby the user
configures the S12XDBG module for a debugging session over the BDM interface. Once configured the
S12XDBG module is armed and the device leaves BDM Mode returning control to the user program,
which is then monitored by the S12XDBG module. Alternatively the S12XDBG module can be configured
over a serial interface using SWI routines.
6.1.1
Freescale Semiconductor
Revision
Number
V03.20
V03.21
V03.22
V03.23
V03.24
V03.25
Data Line
WORD
Term
BDM
DUG
COF
Introduction
Revision Date
Glossary
14 Sep 2007
12 Nov 2007
13 Nov 2007
14 May 2008
23 Oct 2007
04 Jan 2008
Change Of Flow.
Change in the program flow due to a conditional branch, indexed jump or interrupt
Background Debug Mode
Device User Guide, describing the features of the device into which the DBG is integrated
16 bit data entity
64 bit data entity
6.3.2.7/6-203
6.4.2.2/6-216
6.4.2.4/6-217
6.4.5.2/6-221
6.4.5.5/6-225
6.4.5.3/6-223
Sections
Affected
General
S12XS Family Reference Manual, Rev. 1.11
Table 6-2. Glossary Of Terms
Table 6-1. Revision History
- Clarified reserved State Sequencer encodings.
- Added single databyte comparison limitation information
- Added statement about interrupt vector fetches whilst tagging.
- Removed LOOP1 tracing restriction NOTE.
- Added pin reset effect NOTE.
- Text readability improved, typo removed.
- Corrected bit name.
- Updated Revision History Table format. Corrected other paragraph formats.
Definition
Description of Changes
193