S9S12XS256J0CAL Freescale Semiconductor, S9S12XS256J0CAL Datasheet - Page 121

• Manufacturer Part Number: S9S12XS256J0CAL
• Description: MCU 256K FLASH 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S9S12XS256J0CAL

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 8K x 8
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Processor Series: S12XS
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 12 KB
• Interface Type: CAN, SCI, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 12
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: DEMO9S12XSFAME, EVB9S12XEP100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

2.4.2
A set of configuration registers is common to all ports with exception of the ATD port
registers can be written at any time, however a specific configuration might not become active.
For example selecting a pull-up device: This device does not become active while the port is used as a
push-pull output.
1
2.4.2.1
This register holds the value driven out to the pin if the pin is used as a general purpose I/O.
Writing to this register has only an effect on the pin if the pin is used as general purpose output. When
reading this address, the buffered state of the pin is returned if the associated data direction register bit is
set to “0”.
If the data direction register bits are set to logic level “1”, the contents of the data register is returned. This
is independent of any other configuration
2.4.2.2
This is a read-only register and always returns the buffered state of the pin
2.4.2.3
This register defines whether the pin is used as a input or an output.
If a peripheral module controls the pin the contents of the data direction register is ignored
Independent of the pin usage with a peripheral module this register determines the source of data when
reading the associated data register address (2.4.2.1/2-121).
Freescale Semiconductor
Port
Each cell represents one register with individual configuration bits
AD
M
H
A
B
E
K
T
S
P
J
Data
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
Registers
Data register (PORTx, PTx)
Input register (PTIx)
Data direction register (DDRx)
Input
yes
yes
yes
yes
yes
yes
-
-
-
-
-
Direction
Data
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
Table 2-71. Register availability per port
S12XS Family Reference Manual, Rev. 1.11
Reduced
Drive
yes
yes
yes
yes
yes
yes
yes
yes
(Figure
Enable
Pull
yes
yes
yes
yes
yes
yes
yes
yes
2-73).
Polarity
Select
yes
yes
yes
yes
yes
yes
-
-
-
-
-
Or Mode
Wired-
yes
yes
-
-
-
-
-
-
-
-
-
1
Port Integration Module (S12XSPIMV1)
(Figure
Interrupt
Enable
yes
yes
yes
-
-
-
-
-
-
-
-
2-73).
Interrupt
(Table
Flag
yes
yes
yes
-
-
-
-
-
-
-
-
(Figure
2-71). All
Routing
yes
yes
2-73).
-
-
-
-
-
-
-
-
-
121