S9S12XS256J0CAL Freescale Semiconductor, S9S12XS256J0CAL Datasheet - Page 507

• Manufacturer Part Number: S9S12XS256J0CAL
• Description: MCU 256K FLASH 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S9S12XS256J0CAL

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 8K x 8
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Processor Series: S12XS
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 12 KB
• Interface Type: CAN, SCI, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 12
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: DEMO9S12XSFAME, EVB9S12XEP100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 18
256 KByte Flash Module (S12XFTMR256K1V1)
18.1
The FTMR256K1 module implements the following:
The Flash memory is ideal for single-supply applications allowing for field reprogramming without
requiring external high voltage sources for program or erase operations. The Flash module includes a
memory controller that executes commands to modify Flash memory contents. The user interface to the
memory controller consists of the indexed Flash Common Command Object (FCCOB) register which is
written to with the command, global address, data, and any required command parameters. The memory
controller must complete the execution of a command before the FCCOB register can be written to with a
new command.
Freescale Semiconductor
Revision
Number
V01.04
V01.05
V01.06
•
•
256 Kbytes of P-Flash (Program Flash) memory
8 Kbytes of D-Flash (Data Flash) memory
Introduction
19 Dec 2008
25 Sep 2009
03 Jan 2008
Revision
Date
18.4.2.4/18-542
18.4.2.6/18-544
18.4.2.11/18-54
18.4.2.11/18-54
18.4.2.11/18-54
18.3.2.1/18-516
18.4.1.2/18-536
18.3.2/18-514
18.1/18-507
18.6/18-556
Sections
Affected
7
7
7
S12XS Family Reference Manual, Rev. 1.11
Table 18-1. Revision History
- Cosmetic changes
- Clarify single bit fault correction for P-Flash phrase
- Add statement concerning code runaway when executing Read Once,
Program Once, and Verify Backdoor Access Key commands from Flash block
containing associated fields
- Relate Key 0 to associated Backdoor Comparison Key address
- Change “power down reset” to “reset” in
The following changes were made to clarify module behavior related to Flash
register access during reset sequence and while Flash commands are active:
- Add caution concerning register writes while command is active
- Writes to FCLKDIV are allowed during reset sequence while CCIF is clear
- Add caution concerning register writes while command is active
- Writes to FCCOBIX, FCCOBHI, FCCOBLO registers are ignored during
reset sequence
Description of Changes
Section 18.4.2.11
507