HD64F3337YCP16V Renesas Electronics America, HD64F3337YCP16V Datasheet - Page 118

• Manufacturer Part Number: HD64F3337YCP16V
• Description: MCU 3/5V 60K PB-FREE 84-PLCC
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300r

Specifications of HD64F3337YCP16V

• Core Size: 8-Bit
• Program Memory Size: 60KB (60K x 8)
• Oscillator Type: Internal
• Core Processor: H8/300
• Speed: 16MHz
• Connectivity: Host Interface, I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 84-PLCC
• No. Of I/o's: 74
• Ram Memory Size: 1KB
• Cpu Speed: 16MHz
• No. Of Timers: 6
• No. Of Pwm Channels: 2
• Digital Ic Case Style: PLCC
• Controller Family/series: H8/300
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

4.3.6
Table 4.4 indicates the number of states that elapse from an interrupt request signal until the first
instruction of the software interrupt-handling routine is executed. Since on-chip memory is
accessed 16 bits at a time, very fast interrupt service can be obtained by placing interrupt-handling
routines in on-chip ROM and the stack in on-chip RAM.
Table 4.4
No.
1
2
3
4
5
6
Notes: *1 These values do not apply if the current instruction is EEPMOV.
4.3.7
Note that the following type of contention can occur in interrupt handling.
When software clears the enable bit of an interrupt to 0 to disable the interrupt, the interrupt
becomes disabled after execution of the clearing instruction. If an enable bit is cleared by a BCLR
or MOV instruction, for example, and the interrupt is requested during execution of that
instruction, at the instant when the instruction ends the interrupt is still enabled, so after execution
of the instruction, the hardware exception-handling sequence is executed for the interrupt. If a
higher-priority interrupt is requested at the same time, however, the hardware exception-handling
sequence is executed for the higher-priority interrupt and the interrupt that was disabled is ignored.
Similar considerations apply when an interrupt request flag is cleared to 0.
86
*2 If wait states are inserted in external memory access, add the number of wait states.
*3 1 for internal interrupts.
Interrupt Response Time
Precaution
Reason for Wait
Interrupt priority decision
Wait for completion of current
instruction
Save PC and CCR
Fetch vector
Fetch instruction
Internal processing
Total
Number of States before Interrupt Service
*1
On-Chip Memory
2
1 to 13
4
2
4
4
17 to 29
*3
Number of States
External Memory
2
5 to 17
12
6
12
4
41 to 53
*3
*2
*2
*2
*2
*2