HD64F3337YCP16V Renesas Electronics America, HD64F3337YCP16V Datasheet - Page 639

• Manufacturer Part Number: HD64F3337YCP16V
• Description: MCU 3/5V 60K PB-FREE 84-PLCC
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300r

Specifications of HD64F3337YCP16V

• Core Size: 8-Bit
• Program Memory Size: 60KB (60K x 8)
• Oscillator Type: Internal
• Core Processor: H8/300
• Speed: 16MHz
• Connectivity: Host Interface, I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 84-PLCC
• No. Of I/o's: 74
• Ram Memory Size: 1KB
• Cpu Speed: 16MHz
• No. Of Timers: 6
• No. Of Pwm Channels: 2
• Digital Ic Case Style: PLCC
• Controller Family/series: H8/300
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

A.3
The tables below can be used to calculate the number of states required for instruction execution.
Table A.3 indicates the number of states required for each cycle (instruction fetch, branch address
read, stack operation, byte data access, word data access, internal operation). Table A.4 indicates
the number of cycles of each type occurring in each instruction. The total number of states
required for execution of an instruction can be calculated from these two tables as follows:
Execution states = I
Examples: Mode 1 (on-chip ROM disabled), stack located in external memory, 1 wait state
inserted in external memory access.
1. BSET #0, @FFC7
2. JSR @@30
Table A.3
Execution Status
(Instruction Cycle)
Instruction fetch
Branch address read
Stack operation
Byte data access
Word data access
Internal operation
Note: m: Number of wait states inserted in access to external device.
From table A.4: I = L = 2,
From table A.3: S
Number of states required for execution: 2
From table A.4: I = 2,
From table A.3: S
Number of states required for execution: 2
Number of States Required for Execution
Number of States Taken by Each Cycle in Instruction Execution
I
I
S
= 8,
= S
I
S
S
S
S
S
S
+ J S
I
J
K
L
M
N
J
= S
J = K = 1,
S
K
L
J
= 8
+ K S
= 3
On-Chip Memory
2
1
J = K = M = N= 0
K
L = M = N = 0
+ L S
8 + 2 3 = 22
8 + 1 8 + 1 8 = 32
L
+ M S
On-Chip Supporting
Module
6
3
6
1
Access Location
M
+ N S
N
External Device
6 + 2m
3 + m
6 + 2m
1
607