HD64F3337YCP16V Renesas Electronics America, HD64F3337YCP16V Datasheet - Page 192

• Manufacturer Part Number: HD64F3337YCP16V
• Description: MCU 3/5V 60K PB-FREE 84-PLCC
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300r

Specifications of HD64F3337YCP16V

• Core Size: 8-Bit
• Program Memory Size: 60KB (60K x 8)
• Oscillator Type: Internal
• Core Processor: H8/300
• Speed: 16MHz
• Connectivity: Host Interface, I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 84-PLCC
• No. Of I/o's: 74
• Ram Memory Size: 1KB
• Cpu Speed: 16MHz
• No. Of Timers: 6
• No. Of Pwm Channels: 2
• Digital Ic Case Style: PLCC
• Controller Family/series: H8/300
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

8.1.4
Table 8.2 lists the registers of the free-running timer module.
Table 8.2
Name
Timer interrupt enable register
Timer control/status register
Free-running counter (high)
Free-running counter (low)
Output compare register A/B (high)
Output compare register A/B (low)
Timer control register
Timer output compare control register
Input capture register A (high)
Input capture register A (low)
Input capture register B (high)
Input capture register B (low)
Input capture register C (high)
Input capture register C (low)
Input capture register D (high)
Input capture register D (low)
Notes: *1 Software can write a 0 to clear bits 7 to 1, but cannot write a 1 in these bits. Bit 0 can be
160
*2 OCRA and OCRB share the same addresses. Access is controlled by the OCRS
Register Configuration
read and written to.
bit in TOCR.
Register Configuration
*2
*2
Abbreviation
TIER
TCSR
FRC (H)
FRC (L)
OCRA/B (H)
OCRA/B (L)
TCR
TOCR
ICRA (H)
ICRA (L)
ICRB (H)
ICRB (L)
ICRC (H)
ICRC (L)
ICRD (H)
ICRD (L)
R/W
R/W
R/(W)
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
R
R
R
R
R
*1
Initial
Value
H'01
H'00
H'00
H'00
H'FF
H'FF
H'00
H'E0
H'00
H'00
H'00
H'00
H'00
H'00
H'00
H'00
Address
H'FF90
H'FF91
H'FF92
H'FF93
H'FF94
H'FF95
H'FF96
H'FF97
H'FF98
H'FF99
H'FF9A
H'FF9B
H'FF9C
H'FF9D
H'FF9E
H'FF9F
*2
*2