HD64F3337YCP16V Renesas Electronics America, HD64F3337YCP16V Datasheet - Page 259

• Manufacturer Part Number: HD64F3337YCP16V
• Description: MCU 3/5V 60K PB-FREE 84-PLCC
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300r

Specifications of HD64F3337YCP16V

• Core Size: 8-Bit
• Program Memory Size: 60KB (60K x 8)
• Oscillator Type: Internal
• Core Processor: H8/300
• Speed: 16MHz
• Connectivity: Host Interface, I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 84-PLCC
• No. Of I/o's: 74
• Ram Memory Size: 1KB
• Cpu Speed: 16MHz
• No. Of Timers: 6
• No. Of Pwm Channels: 2
• Digital Ic Case Style: PLCC
• Controller Family/series: H8/300
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Bits 2to 0— Clock Select (CKS2–CKS0): These bits select one of eight clock sources obtained
by dividing the system clock (ø).
The overflow interval is the time from when the watchdog timer counter begins counting from
H'00 until an overflow occurs. In interval timer mode, WOVF interrupts are requested at this
interval.
Bit 2:
CKS2
0
1
11.2.3
Only bit 3 is described here. For details of other bits, see section 3.2., System Control Register
(SYSCR), and descriptions of the relevant modules.
Bit 3—External Reset (XRST): Indicates the reset source. When the watchdog timer is used, a
reset can be generated by watchdog timer overflow as well as by external reset input.
XRST is a read-only bit. It is set to 1 by an external reset and cleared to 0 by an internal reset due
to watchdog timer overflow when the RST/NMI bit is 1.
Bit 3: XRST
0
1
Bit
Initial value
Read/Write
System Control Register (SYSCR)
Bit 1:
CKS1
0
1
0
1
SSBY
R/W
Description
A reset is generated by an internal reset due to watchdog timer overflow
A reset is generated by external reset input
7
0
Bit 0:
CKS0
0
1
0
1
0
1
0
1
STS2
R/W
6
0
Description
ø
ø
ø
ø
ø
ø
ø
ø
P
P
P
P
P
P
P
P
STS1
/2
/32
/64
/128
/256
/512
/2048
/4096
R/W
5
0
STS0
R/W
4
0
Overflow Interval (ø
51.2 s
819.2 s
1.6 ms
3.3 ms
6.6 ms
13.1 ms
52.4 ms
104.9 ms
XRST
3
1
R
NMIEG
R/W
2
0
P
= 10 MHz)
R/W
HIE
1
0
(Initial value)
(Initial value)
RAME
R/W
0
1
227