HD64F3337YCP16V Renesas Electronics America, HD64F3337YCP16V Datasheet - Page 328

• Manufacturer Part Number: HD64F3337YCP16V
• Description: MCU 3/5V 60K PB-FREE 84-PLCC
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300r

Specifications of HD64F3337YCP16V

• Core Size: 8-Bit
• Program Memory Size: 60KB (60K x 8)
• Oscillator Type: Internal
• Core Processor: H8/300
• Speed: 16MHz
• Connectivity: Host Interface, I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 84-PLCC
• No. Of I/o's: 74
• Ram Memory Size: 1KB
• Cpu Speed: 16MHz
• No. Of Timers: 6
• No. Of Pwm Channels: 2
• Digital Ic Case Style: PLCC
• Controller Family/series: H8/300
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

DATA: Transferred data. The bit length is set by bits BC2 to BC0 in ICMR. The MSB-first or
P:
13.3.2
In master transmit mode, the master device outputs the transmit clock and transmit data, and the
slave device returns an acknowledge signal. The transmit procedure and operations in master
transmit mode are described below.
1. Set bits MLS and WAIT in ICMR and bits ACK and CKS2 to CKS0 in ICCR according to the
2. Read BBSY in ICSR, check that the bus is free, then set MST and TRS to 1 in ICCR to select
3. Write data in ICDR. The master device outputs the written data together with a sequence of
4. When 1 byte of data has been transmitted, IRIC is set to 1 in ICSR at the rise of the ninth
5. Software clears IRIC to 0 in ICSR.
296
SDA
SCL
operating mode. Set bit ICE in ICCR to 1.
master transmit mode. After that, write 1 in BBSY and 0 in SCP. This generates a start
condition by causing a high-to-low transition of SDA while SCL is high.
transmit clock pulses at the timing shown in figure 13.6. If FS is 0 in SAR, the first byte
following the start condition contains a 7-bit slave address and indicates the transmit/receive
direction. The selected slave device (the device with the matching slave address) drives SDA
low at the ninth transmit clock pulse to acknowledge the data.
transmit clock pulse. If IEIC is set to 1 in ICCR, a CPU interrupt is requested. After one frame
has been transferred, SCL is automatically brought to the low level in synchronization with the
internal clock and held low.
S
acknowledged, set the ACK bit to 1 in ICCR to keep the interface from generating the
acknowledge signal and its clock pulse.
LSB-first format is selected by bit MLS in ICMR.
Stop condition. The master device drives SDA from low to high while SCL is high.
Master Transmit Operation
SLA
1-7
R/W
8
9
A
Figure 13.5 I
1-7
DATA
2
C Bus Timing
8
9
A
1-7
DATA
8
A/A
9
P