HD64F3337YCP16V Renesas Electronics America, HD64F3337YCP16V Datasheet - Page 335

• Manufacturer Part Number: HD64F3337YCP16V
• Description: MCU 3/5V 60K PB-FREE 84-PLCC
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300r

Specifications of HD64F3337YCP16V

• Core Size: 8-Bit
• Program Memory Size: 60KB (60K x 8)
• Oscillator Type: Internal
• Core Processor: H8/300
• Speed: 16MHz
• Connectivity: Host Interface, I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 84-PLCC
• No. Of I/o's: 74
• Ram Memory Size: 1KB
• Cpu Speed: 16MHz
• No. Of Timers: 6
• No. Of Pwm Channels: 2
• Digital Ic Case Style: PLCC
• Controller Family/series: H8/300
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

13.3.6
The interrupt request flag (IRIC) is set at different times depending on the WAIT bit in ICMR and
ACK bit in ICCR. SCL is automatically held low after one frame has been transferred; this timing
is synchronized with the internal clock. Figure 13.10 shows the IRIC set timing and SCL control.
(a) When WAIT = 0 and ACK = 0
(b) When WAIT = 1 and ACK = 0
(c) When ACK = 1
IRIC Set Timing and SCL Control
SCL
SDA
IRIC
User processing
Note: The ICDR write (transmit) or read (receive) following the clearing of IRIC
SCL
SDA
IRIC
User processing
SCL
SDA
IRIC
User processing
should be executed after the rise of SCL (ninth clock pulse).
7
7
7
Figure 13.10 IRIC Set Timing and SCL Control
8
8
8
Clear IRIC
Clear IRIC
Clear IRIC
A
A
Write to ICDR (transmit)
or read ICDR (receive)
Write to ICDR (transmit)
or read ICDR (receive)
Write to ICDR (transmit)
or read ICDR (receive)
1
1
1
303