HD64F3337YCP16V Renesas Electronics America, HD64F3337YCP16V Datasheet - Page 269

• Manufacturer Part Number: HD64F3337YCP16V
• Description: MCU 3/5V 60K PB-FREE 84-PLCC
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300r

Specifications of HD64F3337YCP16V

• Core Size: 8-Bit
• Program Memory Size: 60KB (60K x 8)
• Oscillator Type: Internal
• Core Processor: H8/300
• Speed: 16MHz
• Connectivity: Host Interface, I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 84-PLCC
• No. Of I/o's: 74
• Ram Memory Size: 1KB
• Cpu Speed: 16MHz
• No. Of Timers: 6
• No. Of Pwm Channels: 2
• Digital Ic Case Style: PLCC
• Controller Family/series: H8/300
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

12.2
12.2.1
RSR is a shift register that converts incoming serial data to parallel data. When one data character
has been received, it is transferred to the receive data register (RDR).
The CPU cannot read or write RSR directly.
12.2.2
RDR stores received data. As each character is received, it is transferred from RSR to RDR,
enabling RSR to receive the next character. This double-buffering allows the SCI to receive data
continuously.
RDR is a read-only register. RDR is initialized to H'00 by a reset and in the standby modes.
12.2.3
TSR is a shift register that converts parallel data to serial transmit data. When transmission of one
character is completed, the next character is moved from the transmit data register (TDR) to TSR
and transmission of that character begins. If the TDRE bit is still set to 1, however, nothing is
transferred to TSR.
The CPU cannot read or write TSR directly.
Bit
Read/Write
Bit
Initial value
Read/Write
Bit
Read/Write
Register Descriptions
Receive Shift Register (RSR)
Receive Data Register (RDR)
Transmit Shift Register (TSR)
—
—
7
7
0
R
7
—
—
6
6
0
R
6
—
—
5
5
0
R
5
—
—
4
4
0
R
4
—
—
3
3
0
R
3
—
—
2
2
0
R
2
—
—
1
1
0
R
1
—
—
0
0
0
R
0
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