HD64F3337YCP16V Renesas Electronics America, HD64F3337YCP16V Datasheet - Page 545

• Manufacturer Part Number: HD64F3337YCP16V
• Description: MCU 3/5V 60K PB-FREE 84-PLCC
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300r

Specifications of HD64F3337YCP16V

• Core Size: 8-Bit
• Program Memory Size: 60KB (60K x 8)
• Oscillator Type: Internal
• Core Processor: H8/300
• Speed: 16MHz
• Connectivity: Host Interface, I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 84-PLCC
• No. Of I/o's: 74
• Ram Memory Size: 1KB
• Cpu Speed: 16MHz
• No. Of Timers: 6
• No. Of Pwm Channels: 2
• Digital Ic Case Style: PLCC
• Controller Family/series: H8/300
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Notes on Use of Boot Mode
1. When the H8/3337SF comes out of reset in boot mode, it measures the low period of the input
2. In boot mode, if any data has been programmed into the flash memory (if all data is not H'FF),
3. Interrupts cannot be used while the flash memory is being programmed or erased.
4. The RxD
5. Before branching to the user program (at address H'E880 in the RAM area), the H8/3337SF
Note: * This area cannot be used until the H8/3337SF starts to execute the user program
at the SCI’s RxD
100 states for the H8/3337SF to get ready to measure the low period of the RxD
all flash memory blocks are erased. Boot mode is for use when user programming mode is
unavailable, such as the first time on-board programming is performed, or if the program
activated in user programming mode is accidentally erased.
terminates transmit and receive operations by the on-chip SCI (by clearing the RE and TE bits
of serial control register SCR to 0 in channel 1), but the auto-aligned bit rate remains set in bit
rate register BRR. The transmit data output pin (TxD
P8
4
DDR of the port 8 data direction register and P8
transferred to RAM. Note that even after the branch to the user program, the boot
program area still contains the boot program.
1
and TxD
1
pin. The reset should end with RxD
1
pins should be pulled up on-board.
Figure 21.9 RAM Areas in Boot Mode
H'F780
H'FDFF
H'FF00
H'FF7F
User program
Boot program
transfer area
(1664 bytes)
(128 bytes)
area*
4
DR of the port 8 data register are set to 1).
1
) is in the high output state (in port 8, bits
1
high. After the reset ends, it takes about
1
input.
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