HD64F3337YCP16V Renesas Electronics America, HD64F3337YCP16V Datasheet - Page 323

• Manufacturer Part Number: HD64F3337YCP16V
• Description: MCU 3/5V 60K PB-FREE 84-PLCC
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300r

Specifications of HD64F3337YCP16V

• Core Size: 8-Bit
• Program Memory Size: 60KB (60K x 8)
• Oscillator Type: Internal
• Core Processor: H8/300
• Speed: 16MHz
• Connectivity: Host Interface, I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 84-PLCC
• No. Of I/o's: 74
• Ram Memory Size: 1KB
• Cpu Speed: 16MHz
• No. Of Timers: 6
• No. Of Pwm Channels: 2
• Digital Ic Case Style: PLCC
• Controller Family/series: H8/300
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Bit 6—I
has issued an interrupt request to the CPU. IRIC is set to 1 at the end of a data transfer, when a
slave address or general call address is detected in slave receive mode, and when bus arbitration is
lost in master transmit mode. IRIC is set at different timings depending on the ACK bit in ICCR
and WAIT bit in ICMR. See the item on IRIC Set Timing and SCL Control in section 13.3.6.
IRIC is cleared by reading IRIC after it has been set to 1, then writing 0 in IRIC.
Bit 6: IRIC
0
1
Bit 5—Start Condition/Stop Condition Prohibit (SCP): Controls the issuing of start and stop
conditions in master mode. To issue a start condition, write 1 in BBSY and 0 in SCP. A start
condition for retransmit is issued in the same way. To issue a stop condition, write 0 in BBSY and
0 in SCP. This bit always reads 1. Written data is not stored.
Bit 5: SCP
0
1
Bit 4—Reserved: This bit cannot be modified and is always read as 1.
2
C Bus Interface Interrupt Request Flag (IRIC): Indicates that the I
Description
Waiting for transfer, or transfer in progress
To clear this bit, the CPU must read IRIC when IRIC = 1, then write 0 in IRIC
Interrupt requested
This bit is set to 1 at the following times:
Master mode
Slave mode (when FS = 0)
Slave mode (when FS = 1)
Description
Writing 0 issues a start or stop condition, in combination with BBSY
Reading always results in 1
Writing is ignored
End of data transfer
When bus arbitration is lost
When the slave address is matched, and whenever a data transfer ends
after that, until a retransmit start condition or a stop condition is detected
When a general call address is detected, and whenever a data transfer
ends after that, until a retransmit start condition or a stop condition is
detected
End of data transfer
2
C bus interface
(Initial value)
(Initial value)
291