HD64F3337YCP16V Renesas Electronics America, HD64F3337YCP16V Datasheet - Page 352

• Manufacturer Part Number: HD64F3337YCP16V
• Description: MCU 3/5V 60K PB-FREE 84-PLCC
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300r

Specifications of HD64F3337YCP16V

• Core Size: 8-Bit
• Program Memory Size: 60KB (60K x 8)
• Oscillator Type: Internal
• Core Processor: H8/300
• Speed: 16MHz
• Connectivity: Host Interface, I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 84-PLCC
• No. Of I/o's: 74
• Ram Memory Size: 1KB
• Cpu Speed: 16MHz
• No. Of Timers: 6
• No. Of Pwm Channels: 2
• Digital Ic Case Style: PLCC
• Controller Family/series: H8/300
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Bit 2—Input Buffer Full Interrupt Enable 2 (IBFIE2): Enables or disables the IBF2 interrupt
to the slave CPU.
Bit 2: IBFIE2
0
1
Bit 1— Input Buffer Full Interrupt Enable 1 (IBFIE1): Enables or disables the IBF1 interrupt
to the slave CPU.
Bit 1: IBFIE1
0
1
Bit 0—Fast Gate A
fast A
manipulate the P8
Bit 0: FGA20E
0
1
14.2.3
Bit
Initial value
Slave Read/Write
Host Read/Write
IDR1 is an 8-bit read-only register to the slave processor, and an 8-bit write-only register to the
host processor. When CS
rising edge of IOW. The HA
written information is a command or data.
The initial values of IDR1 after a reset or standby are undetermined.
320
20
gate is disabled, a regular-speed A
Input Data Register 1 (IDR1)
1
output.
Description
IDR2 input buffer full interrupt is disabled
IDR2 input buffer full interrupt is enabled
Description
IDR1 input buffer full interrupt is disabled
IDR1 input buffer full interrupt is enabled
Description
Disables fast A
Enables fast A
20
IDR7
—
W
R
Enable (FGA20E): Enables or disables the fast A
7
1
is low, information on the host data bus is written into IDR1 at the
0
state is also latched into the C/D bit in STR1 to indicate whether the
IDR6
—
W
R
6
20
20
gate function
gate function
IDR5
—
W
R
20
5
gate signal can be implemented by using software to
IDR4
—
W
R
4
IDR3
—
W
R
3
IDR2
20
—
W
R
2
gate function. When the
IDR1
—
W
R
1
(Initial value)
(Initial value)
(Initial value)
IDR0
—
W
R
0