HD64F3337YCP16V Renesas Electronics America, HD64F3337YCP16V Datasheet - Page 354

• Manufacturer Part Number: HD64F3337YCP16V
• Description: MCU 3/5V 60K PB-FREE 84-PLCC
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300r

Specifications of HD64F3337YCP16V

• Core Size: 8-Bit
• Program Memory Size: 60KB (60K x 8)
• Oscillator Type: Internal
• Core Processor: H8/300
• Speed: 16MHz
• Connectivity: Host Interface, I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 84-PLCC
• No. Of I/o's: 74
• Ram Memory Size: 1KB
• Cpu Speed: 16MHz
• No. Of Timers: 6
• No. Of Pwm Channels: 2
• Digital Ic Case Style: PLCC
• Controller Family/series: H8/300
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Bit 1—Input Buffer Full (IBF): Set to 1 when the host processor writes to IDR1. This bit is an
internal interrupt source to the slave processor. IBF is cleared to 0 when the slave processor reads
IDR1.
Bit 1: IBF
0
1
Bit 0—Output Buffer Full (OBF): Set to 1 when the slave processor writes to ODR1. Cleared to
0 when the host processor reads ODR1.
Bit 0: OBF
0
1
Table 14.3 shows the conditions for setting and clearing the STR1 flags.
Table 14.3 Set/Clear Timing for STR1 Flags
Flag
C/D
IBF
OBF
14.2.6
Bit
Initial value
Slave Read/Write
Host Read/Write
IDR2 is an 8-bit read-only register to the slave processor, and an 8-bit write-only register to the
host processor. When CS
rising edge of IOW. The HA
written information is a command or data.
The initial values of IDR2 after a reset or standby are undetermined.
322
Input Data Register 2 (IDR2)
Setting Condition
Rising edge of host’s write signal (IOW)
when HA
Rising edge of host’s write signal (IOW)
when writing to IDR1
Falling edge of slave’s internal write
signal (WR) when writing to ODR1
Description
This bit is cleared when the slave processor reads IDR1
This bit is set when the host processor writes to IDR1
Description
This bit is cleared when the host processor reads ODR1
This bit is set when the slave processor writes to ODR1
IDR7
0
—
W
is high
R
7
2
is low, information on the host data bus is written into IDR2 at the
0
state is also latched into the C/D bit in STR2 to indicate whether the
IDR6
—
W
R
6
IDR5
—
W
R
5
IDR4
—
W
R
4
Clearing Condition
Rising edge of host’s write signal (IOW)
when HA
Falling edge of slave’s internal read signal
(RD) when reading IDR1
Rising edge of host’s read signal (IOR)
when reading ODR1
IDR3
—
W
R
3
0
is low
IDR2
—
W
R
2
IDR1
—
W
R
1
(Initial value)
(Initial value)
IDR0
—
W
R
0