HD64F3337YCP16V Renesas Electronics America, HD64F3337YCP16V Datasheet - Page 306

• Manufacturer Part Number: HD64F3337YCP16V
• Description: MCU 3/5V 60K PB-FREE 84-PLCC
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300r

Specifications of HD64F3337YCP16V

• Core Size: 8-Bit
• Program Memory Size: 60KB (60K x 8)
• Oscillator Type: Internal
• Core Processor: H8/300
• Speed: 16MHz
• Connectivity: Host Interface, I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 84-PLCC
• No. Of I/o's: 74
• Ram Memory Size: 1KB
• Cpu Speed: 16MHz
• No. Of Timers: 6
• No. Of Pwm Channels: 2
• Digital Ic Case Style: PLCC
• Controller Family/series: H8/300
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

In transmitting serial data, the SCI operates as follows.
1. The SCI monitors the TDRE bit in SSR. When TDRE is cleared to 0 the SCI recognizes that
2. After loading the data from TDR into TSR, the SCI sets the TDRE bit to 1 and starts
3. The SCI checks the TDRE bit when it outputs the MSB (bit 7). If TDRE is 0, the SCI loads
4. After the end of serial transmission, the SCK pin is held at the high level.
Figure 12.14 shows an example of SCI transmit operation.
274
Serial data
TDRE
TEND
Serial clock
the transmit data register (TDR) contains new data, and loads this data from TDR into the
transmit shift register (TSR).
transmitting. If the TIE bit (TDR-empty interrupt enable) in SCR is set to 1, the SCI requests a
TXI interrupt (TDR-empty interrupt) at this time.
If clock output is selected the SCI outputs eight serial clock pulses, triggered by the clearing of
the TDRE bit to 0. If an external clock source is selected, the SCI outputs data in
synchronization with the input clock.
Data is output from the TxD pin in order from LSB (bit 0) to MSB (bit 7).
data from TDR into TSR, then begins serial transmission of the next frame. If TDRE is 1, the
SCI sets the TEND bit in SSR to 1, transmits the MSB, then holds the output in the MSB state.
If the TEIE bit (transmit-end interrupt enable) in SCR is set to 1, a TEI interrupt (TSR-empty
interrupt) is requested at this time.
TXI
request
Figure 12.14 Example of SCI Transmit Operation
Bit 0
TXI interrupt
handler writes
data in TDR and
clears TDRE to 0
Bit 1
1 frame
TXI
request
Bit 7
Bit 0
Bit 1
Bit 6
TEI
request
Bit 7