HD64F3337YCP16V Renesas Electronics America, HD64F3337YCP16V Datasheet - Page 212

• Manufacturer Part Number: HD64F3337YCP16V
• Description: MCU 3/5V 60K PB-FREE 84-PLCC
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300r

Specifications of HD64F3337YCP16V

• Core Size: 8-Bit
• Program Memory Size: 60KB (60K x 8)
• Oscillator Type: Internal
• Core Processor: H8/300
• Speed: 16MHz
• Connectivity: Host Interface, I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 84-PLCC
• No. Of I/o's: 74
• Ram Memory Size: 1KB
• Cpu Speed: 16MHz
• No. Of Timers: 6
• No. Of Pwm Channels: 2
• Digital Ic Case Style: PLCC
• Controller Family/series: H8/300
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

When ICRC or ICRD is used as a buffer register, its input capture flag is set by the selected
transition of its input capture signal. For example, if ICRC is used to buffer ICRA, when the edge
transition selected by the IEDGC bit occurs on the FTIC input capture line, ICFC will be set, and
if the ICIEC bit is set, an interrupt will be requested. The FRC value will not be transferred to
ICRC, however.
In buffered input capture, if the upper byte of either of the two registers to which data will be
transferred (ICRA and ICRC, or ICRB and ICRD) is being read when the input signal arrives,
input capture is delayed by one system clock (ø). Figure 8.11 shows the timing when BUFEA = 1.
180
ø
Input at
FTIA pin
Internal input
capture signal
Figure 8.11 Input Capture Timing (1-State Delay, Buffer Mode)
CPU reads upper byte of ICRA or ICRC
T
1
Read cycle:
T
2
T
3