WM8352GEB/V Wolfson Microelectronics, WM8352GEB/V Datasheet - Page 105

• Manufacturer Part Number: WM8352GEB/V
• Description: Audio CODECs Audio CODEC plus pwr management
• Manufacturer: Wolfson Microelectronics

Specifications of WM8352GEB/V

• Number Of Adc Inputs: 2
• Number Of Dac Outputs: 2
• Conversion Rate: 48 KSPS
• Interface Type: Serial (2-Wire, 3-Wire, 4-Wire)
• Resolution: 12 bit
• Operating Supply Voltage: 3.7 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: BGA
• Minimum Operating Temperature: - 25 C
• Number Of Channels: 2 ADC/2 DAC
• Supply Current: 260 uA
• Thd Plus Noise: - 83 dB
• Audio Codec Type: Stereo
• No. Of Adcs: 2
• No. Of Dacs: 2
• No. Of Input Channels: 8
• No. Of Output Channels: 6
• Adc / Dac Resolution: 24bit
• Adcs / Dacs Signal To Noise Ratio: 95dB
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Production Data
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13.12.6 ZERO CROSS TIMEOUT
A zero-cross timeout function is also provided so that if zero cross is enabled on the input or output
PGAs the gain will automatically update after a timeout period if a zero cross has not occurred.
The zero-cross timeout function requires the internal slow clock to be enabled - see Section 12.3.6.
13.12.7 INTERRUPTS AND FAULT PROTECTION
The CODEC has its own first-level interrupt, CODEC_INT (see Section 24). This comprises four
second-level interrupts which indicate Jack detect and Microphone current conditions. These
interrupts can be individually masked by setting the applicable mask bit(s) as described in Table 53.
R31 (1Fh)
Comparator
Interrupt
Status
R39 (27h)
Comparator
Interrupt
Status Mask
Table 53 CODEC Interrupts
ADDRESS
11:8
BIT
11
10
9
8
CODEC_JCK_DET_L_EINT
CODEC_JCK_DET_R_EINT
CODEC_MICSCD_EINT
CODEC_MICD_EINT
“IM_” + name of respective
bit in R31
LABEL
Left channel Jack detection interrupt.
(Rising and Falling Edge triggered)
Note: This bit is cleared once read.
Right channel Jack detection interrupt.
(Rising and Falling Edge triggered)
Note: This bit is cleared once read.
Mic short-circuit detect interrupt.
(Rising and Falling Edge triggered)
Note: This bit is cleared once read.
Mic detect interrupt.
(Rising and Falling Edge triggered)
Note: This bit is cleared once read.
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Each bit in R39 enables or masks the
corresponding bit in R31. The default
value for these bits is 0 (unmasked).
DESCRIPTION
PD, March 2010, Rev 4.2
WM8352
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