WM8352GEB/V Wolfson Microelectronics, WM8352GEB/V Datasheet - Page 91

• Manufacturer Part Number: WM8352GEB/V
• Description: Audio CODECs Audio CODEC plus pwr management
• Manufacturer: Wolfson Microelectronics

Specifications of WM8352GEB/V

• Number Of Adc Inputs: 2
• Number Of Dac Outputs: 2
• Conversion Rate: 48 KSPS
• Interface Type: Serial (2-Wire, 3-Wire, 4-Wire)
• Resolution: 12 bit
• Operating Supply Voltage: 3.7 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: BGA
• Minimum Operating Temperature: - 25 C
• Number Of Channels: 2 ADC/2 DAC
• Supply Current: 260 uA
• Thd Plus Noise: - 83 dB
• Audio Codec Type: Stereo
• No. Of Adcs: 2
• No. Of Dacs: 2
• No. Of Input Channels: 8
• No. Of Output Channels: 6
• Adc / Dac Resolution: 24bit
• Adcs / Dacs Signal To Noise Ratio: 95dB
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Production Data
13.10 DIGITAL AUDIO INTERFACE
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The audio interface enables the WM8352 to exchange audio data with other system components. It
is separate from the control interface and has four dedicated pins:
The LRCLK and BCLK pins are outputs when the WM8352 operates as a master device and are
inputs when it is a slave device.
In order to allow the ADC and DAC to run at different sampling rates, separate ADCLRCLK and
ADCBCLK signals are both available through GPIO pins: GPIO5 (ADCLRCLK) and GPIO6 or GPIO8
(ADCBCLK). This feature also allows mixed Master/Slave operation between the ADC and DAC.
13.10.1 AUDIO DATA FORMATS
The audio interface supports six different audio data formats:
In all of these formats, the MSB (most significant bit) of each data sample is transferred first and the
LSB (least significant bit) last.
R112 (70h)
Audio
Interface
ADDRESS










ADCDAT: Output pin for data coming from the audio ADC
DACDAT: Input pin for audio data going to the audio DAC
LRCLK: Data Left/Right alignment clock (also known as “word clock”)
BCLK: Bit clock, for synchronisation
Left justified
Right justified
I
DSP mode A
DSP mode B
TDM Mode
2
S
11:10
BIT
15
13
12
AIF_BCLK_INV
AIF_TRI
AIF_LRCLK_IN
V
AIF_WL [1:0]
LABEL
DEFAULT
(24 bits)
10
0
0
0
BCLK polarity
0 = normal
1 = inverted
Sets Output enables for LRCLK and
BCLK and ADCDAT to inactive state
0 = normal
1 = forces pins to Hi-Z
LRCLK clock polarity
0 = normal
1 = inverted
DSP Mode – mode A/B select
0 = MSB is available on 2
edge after LRCLK rising edge (mode A)
1 = MSB is available on 1
edge after LRCLK rising edge (mode B)
Data word length
11 = 32 bits
10 = 24 bits
01 = 20 bits
00 = 16 bits
Note: When using the Right-Justified
data format (AIF_FMT=00), the
maximum word length is 24 bits.
DESCRIPTION
PD, March 2010, Rev 4.2
nd
st
BCLK rising
BCLK rising
WM8352
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