WM8352GEB/V Wolfson Microelectronics, WM8352GEB/V Datasheet - Page 49

• Manufacturer Part Number: WM8352GEB/V
• Description: Audio CODECs Audio CODEC plus pwr management
• Manufacturer: Wolfson Microelectronics

Specifications of WM8352GEB/V

• Number Of Adc Inputs: 2
• Number Of Dac Outputs: 2
• Conversion Rate: 48 KSPS
• Interface Type: Serial (2-Wire, 3-Wire, 4-Wire)
• Resolution: 12 bit
• Operating Supply Voltage: 3.7 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: BGA
• Minimum Operating Temperature: - 25 C
• Number Of Channels: 2 ADC/2 DAC
• Supply Current: 260 uA
• Thd Plus Noise: - 83 dB
• Audio Codec Type: Stereo
• No. Of Adcs: 2
• No. Of Dacs: 2
• No. Of Input Channels: 8
• No. Of Output Channels: 6
• Adc / Dac Resolution: 24bit
• Adcs / Dacs Signal To Noise Ratio: 95dB
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Production Data
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12.3.1
The MCLK_SEL bit is used to select the source for SYSCLK. The source may be either directly from
the MCLK input or may be from the output of the FLL. If required, the selected source may be divided
by two, as determined by MCLK_DIV, as described in Table 8. For further details of the FLL, see
Section 12.4.
When the internal clock source is switched from one value to another using MCLK_SEL, the change
of source will only occur following a falling edge of the source signal that was originally selected. In
the case where the clock source is switched from FLL to MCLK, a suitable falling edge can be
ensured by disabling the FLL after selection of MCLK as the source.
The recommended sequence of actions to switch from FLL to MCLK source is as follows:
Note that, as an alternative to the above sequence, a software reset may be used to re-select MCLK
as the default SYSCLK source.
The recommended sequence of actions to switch from MCLK to FLL source is as follows:
Table 8 SYSCLK Control
R40 (28h)
Clock Control
1
REGISTER
ADDRESS






SYSCLK CONTROL
Select MCLK as source (MCLK_SEL = 0)
Disable FLL (FLL_ENA = 0)
Disable FLL oscillator (FLL_OSC_ENA = 0)
Enable FLL oscillator (FLL_OSC_ENA = 1)
Enable FLL (FLL_ENA = 1)
Select FLL as source (MCLK_SEL = 1)
BIT
11
8
MCLK_SEL
MCLK_DIV
LABEL
DEFAULT
0
0
Selects source for SYSCLK to CODEC
0 = MCLK pin
1 = FLL
Selects MCLK division in slave (MCLK
input) mode:
0 = divide MCLK by 1
1 = divide MCLK by 2
DESCRIPTION
PD, March 2010, Rev 4.2
WM8352
49