WM8352GEB/V Wolfson Microelectronics, WM8352GEB/V Datasheet - Page 201

• Manufacturer Part Number: WM8352GEB/V
• Description: Audio CODECs Audio CODEC plus pwr management
• Manufacturer: Wolfson Microelectronics

Specifications of WM8352GEB/V

• Number Of Adc Inputs: 2
• Number Of Dac Outputs: 2
• Conversion Rate: 48 KSPS
• Interface Type: Serial (2-Wire, 3-Wire, 4-Wire)
• Resolution: 12 bit
• Operating Supply Voltage: 3.7 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: BGA
• Minimum Operating Temperature: - 25 C
• Number Of Channels: 2 ADC/2 DAC
• Supply Current: 260 uA
• Thd Plus Noise: - 83 dB
• Audio Codec Type: Stereo
• No. Of Adcs: 2
• No. Of Dacs: 2
• No. Of Input Channels: 8
• No. Of Output Channels: 6
• Adc / Dac Resolution: 24bit
• Adcs / Dacs Signal To Noise Ratio: 95dB
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Production Data
w
R36 (24h)
Under Voltage
Interrupt Mask
Table 143 Under-Voltage Interrupts
24.3.3
The first-level CS_INT interrupt comprises two second-level interrupts for the Current Sink functions.
Each of these has a status bit in Register R26 and a mask bit in Register R34, as defined in Table
144.
R26 (1Ah)
Interrupt Status
2
R34 (22h)
Interrupt Status
2 Mask
Table 144 Current Sink Interrupts
ADDRESS
ADDRESS
CURRENT SINK (LED DRIVER) INTERRUPTS
13:12
11:0
BIT
BIT
13
12
0
UV_DC1_EINT
“IM_” + name of respective bit
in R28
CS1_EINT
CS2_EINT
“IM_” + name of respective
bit in R26
LABEL
LABEL
DCDC1 Under-voltage interrupt.
(Rising Edge triggered)
Note: This bit is cleared once read.
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Each bit in R36 enables or masks the
corresponding bit in R28. The default
value for these bits is 0 (unmasked).
Flag to indicate drain voltage can no
longer be regulated and output current
may be out of spec.
(Rising Edge triggered)
Note: This bit is cleared once read.
Flag to indicate drain voltage can no
longer be regulated and output current
may be out of spec.
(Rising Edge triggered)
Note: This bit is cleared once read.
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Each bit in R34 enables or masks the
corresponding bit in R26. The default
value for these bits is 0 (unmasked).
DESCRIPTION
DESCRIPTION
PD, March 2010, Rev 4.2
WM8352
201