WM8352GEB/V Wolfson Microelectronics, WM8352GEB/V Datasheet - Page 43
![Audio CODECs Audio CODEC plus pwr management](/photos/16/2/160230/lpwolfsonwm8352_sml.jpg)
WM8352GEB/V
Manufacturer Part Number
WM8352GEB/V
Description
Audio CODECs Audio CODEC plus pwr management
Manufacturer
Wolfson Microelectronics
Datasheet
1.WM8352GEBV.pdf
(335 pages)
Specifications of WM8352GEB/V
Number Of Adc Inputs
2
Number Of Dac Outputs
2
Conversion Rate
48 KSPS
Interface Type
Serial (2-Wire, 3-Wire, 4-Wire)
Resolution
12 bit
Operating Supply Voltage
3.7 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
BGA
Minimum Operating Temperature
- 25 C
Number Of Channels
2 ADC/2 DAC
Supply Current
260 uA
Thd Plus Noise
- 83 dB
Audio Codec Type
Stereo
No. Of Adcs
2
No. Of Dacs
2
No. Of Input Channels
8
No. Of Output Channels
6
Adc / Dac Resolution
24bit
Adcs / Dacs Signal To Noise Ratio
95dB
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Production Data
11.5 4-WIRE SERIAL CONTROL MODE
Figure 31 4-Wire Readback (CMOS)
Figure 32 4-Wire Readback (Open Drain)
w
SDATA
SDOUT
SDATA
SDOUT
SCLK
SCLK
CSB
CSB
R/W
R/W
A6
A6
A5
A5
control register address
control register address
undriven
A4
A4
The 4-wire control interface uses the CSB, SCLK, SDATA and SDOUT pins, which are referenced to
the digital buffer supply, DBVDD. (In 4-wire mode, SDOUT is provided on GPIO6; CSB is provided
on GPIO7.)
4-wire control mode is selected by setting SPI_3WIRE = 1 and SPI_4WIRE = 1.
The Data Output pin, SDOUT, can be configured as CMOS or Open Drain, as described in Table 1.
In CMOS mode, SDOUT is driven low when not outputting register data bits. In Open Drain mode,
SDOUT is undriven when not outputting register data bits.
In Write operations (R/W=0), this mode is the same as 3-wire mode described above.
In Read operations (R/W=1), the SDATA pin is ignored following receipt of the valid register address.
SDOUT is driven by the WM8352.
The 4-wire control mode timing is illustrated in Figure 31 and Figure 32.
A3
A3
A2
A2
A1
A1
A0
A0
B15
B15
B15
B15
B14
B14
B14
B14
B13
B13
B13
B13
B12
B12
B12
B12
B11
B11
B11
B11
control register data bits (READ/WRITE)
control register data bits (READ/WRITE)
B10
B10
B10
B10
B9
B9
B9
B9
B8
B8
B8
B8
B7
B7
B7
B7
B6
B6
B6
B6
B5
B5
B5
B5
B4
B4
B4
B4
B3
B3
B3
B3
PD, March 2010, Rev 4.2
B2
B2
B2
B2
B1
B1
B1
B1
WM8352
B0
B0
B0
B0
ud
43
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