WM8352GEB/V Wolfson Microelectronics, WM8352GEB/V Datasheet - Page 199

• Manufacturer Part Number: WM8352GEB/V
• Description: Audio CODECs Audio CODEC plus pwr management
• Manufacturer: Wolfson Microelectronics

Specifications of WM8352GEB/V

• Number Of Adc Inputs: 2
• Number Of Dac Outputs: 2
• Conversion Rate: 48 KSPS
• Interface Type: Serial (2-Wire, 3-Wire, 4-Wire)
• Resolution: 12 bit
• Operating Supply Voltage: 3.7 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: BGA
• Minimum Operating Temperature: - 25 C
• Number Of Channels: 2 ADC/2 DAC
• Supply Current: 260 uA
• Thd Plus Noise: - 83 dB
• Audio Codec Type: Stereo
• No. Of Adcs: 2
• No. Of Dacs: 2
• No. Of Input Channels: 8
• No. Of Output Channels: 6
• Adc / Dac Resolution: 24bit
• Adcs / Dacs Signal To Noise Ratio: 95dB
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Production Data
24.2 FIRST-LEVEL INTERRUPTS
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Each first level interrupt has a status bit in Register R24, which can be read to determine the origin of
an IRQ event.
Each of these bits may be masked by setting the corresponding field in Register R32. By default, the
first-level interrupts are all masked.
R24 (18h)
System
Interrupts
R32 (20h)
System
Interrupt Mask
Note: Register is R24 is read-only.
Table 141 First Level Interrupt Status and Mask Bits
ADDRESS
13:0
BIT
13
12
9
8
7
6
5
4
3
2
1
0
OC_INT
UV_INT
CS_INT
EXT_INT
CODEC_INT
GP_INT
AUXADC_INT
RTC_INT
SYS_INT
CHG_INT
USB_INT
WKUP_INT
“IM_” + name of respective
bit in R25
LABEL
First-level over-current interrupt.
Note: This bit is cleared once read.
First-level under-voltage interrupt.
Note: This bit is cleared once read.
First-level current sink interrupt.
Note: This bit is cleared once read.
First-level external interrupt.
Note: This bit is cleared once read.
First-level codec interrupt.
Note: This bit is cleared once read.
First-level GPIO interrupt.
Note: This bit is cleared once read.
First-level AUXADC comparator interrupt.
Note: This bit is cleared once read.
First-level RTC interrupt.
Note: This bit is cleared once read.
First-level system interrupt.
Note: This bit is cleared once read.
First-level charger interrupt.
Note: This bit is cleared once read.
First-level USB interrupt.
Note: This bit is cleared once read.
First-level wakeup interrupt.
Note: This bit is cleared once read.
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Each bit in R32 enables or masks the
corresponding bit in R24.
The default value for these bits is 1
(masked)
DESCRIPTION
PD, March 2010, Rev 4.2
WM8352
199