WM8352GEB/V Wolfson Microelectronics, WM8352GEB/V Datasheet - Page 200

• Manufacturer Part Number: WM8352GEB/V
• Description: Audio CODECs Audio CODEC plus pwr management
• Manufacturer: Wolfson Microelectronics

Specifications of WM8352GEB/V

• Number Of Adc Inputs: 2
• Number Of Dac Outputs: 2
• Conversion Rate: 48 KSPS
• Interface Type: Serial (2-Wire, 3-Wire, 4-Wire)
• Resolution: 12 bit
• Operating Supply Voltage: 3.7 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: BGA
• Minimum Operating Temperature: - 25 C
• Number Of Channels: 2 ADC/2 DAC
• Supply Current: 260 uA
• Thd Plus Noise: - 83 dB
• Audio Codec Type: Stereo
• No. Of Adcs: 2
• No. Of Dacs: 2
• No. Of Input Channels: 8
• No. Of Output Channels: 6
• Adc / Dac Resolution: 24bit
• Adcs / Dacs Signal To Noise Ratio: 95dB
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

WM8352
24.3 SECOND-LEVEL INTERRUPTS
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The following sections define the second-level interrupt status and control bits associated with each
of the first-level bits defined in Table 141.
24.3.1
The first-level OC_INT interrupt comprises one second-level interrupt for the limit switch. This status
bit is in Register R29 and its mask bit is in Register R37, as defined in Table 142.
R29 (1Dh)
Over Current
Interrupt
Status
R37 (25h)
Over Current
Interrupt Mask
Table 142 Over-Current Interrupt
24.3.2
The first-level UV_INT interrupt comprises several second-level interrupts for the DC-DCs and LDOs.
Each of these has a status bit in Register R28 and a mask bit in Register R36, as defined in Table
143.
R28 (1Ch)
Under Voltage
Interrupt
Status
ADDRESS
ADDRESS
OVERCURRENT INTERRUPT
UNDERVOLTAGE INTERRUPTS
BIT
BIT
15
15
11
10
9
8
5
4
3
2
1
OC_LS_EINT
IM_OC_LS_EINT
UV_LDO4_EINT
UV_LDO3_EINT
UV_LDO2_EINT
UV_LDO1_EINT
UV_DC6_EINT
UV_DC5_EINT
UV_DC4_EINT
UV_DC3_EINT
UV_DC2_EINT
LABEL
LABEL
Limit Switch Over-current interrupt.
(Rising Edge triggered)
Note: This bit is cleared once read.
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
When IM_OC_LS_EINT is set to 1, then
OC_LS_EINT in R29 does not trigger an
OC_INT interrupt when set. The default
value is 0 (unmasked).
LDO4 Under-voltage interrupt.
(Rising Edge triggered)
Note: This bit is cleared once read.
LDO3 Under-voltage interrupt.
(Rising Edge triggered)
Note: This bit is cleared once read.
LDO2 Under-voltage interrupt.
(Rising Edge triggered)
Note: This bit is cleared once read.
LDO1 Under-voltage interrupt.
(Rising Edge triggered)
Note: This bit is cleared once read.
DCDC6 Under-voltage interrupt.
(Rising Edge triggered)
Note: This bit is cleared once read.
DCDC5 Under-voltage interrupt.
(Rising Edge triggered)
Note: This bit is cleared once read.
DCDC4 Under-voltage interrupt.
(Rising Edge triggered)
Note: This bit is cleared once read.
DCDC3 Under-voltage interrupt.
(Rising Edge triggered)
Note: This bit is cleared once read.
DCDC2 Under-voltage interrupt.
(Rising Edge triggered)
Note: This bit is cleared once read.
PD, March 2010, Rev 4.2
DESCRIPTION
DESCRIPTION
Production Data
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