WM8352GEB/V Wolfson Microelectronics, WM8352GEB/V Datasheet - Page 202

• Manufacturer Part Number: WM8352GEB/V
• Description: Audio CODECs Audio CODEC plus pwr management
• Manufacturer: Wolfson Microelectronics

Specifications of WM8352GEB/V

• Number Of Adc Inputs: 2
• Number Of Dac Outputs: 2
• Conversion Rate: 48 KSPS
• Interface Type: Serial (2-Wire, 3-Wire, 4-Wire)
• Resolution: 12 bit
• Operating Supply Voltage: 3.7 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: BGA
• Minimum Operating Temperature: - 25 C
• Number Of Channels: 2 ADC/2 DAC
• Supply Current: 260 uA
• Thd Plus Noise: - 83 dB
• Audio Codec Type: Stereo
• No. Of Adcs: 2
• No. Of Dacs: 2
• No. Of Input Channels: 8
• No. Of Output Channels: 6
• Adc / Dac Resolution: 24bit
• Adcs / Dacs Signal To Noise Ratio: 95dB
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

WM8352
w
24.3.4
The first-level EXT_INT interrupt comprises three second-level interrupts for USB, Wall and Battery
supply status. Each of these has a status bit in Register R31 and a mask bit in Register R37, as
defined in Table 145. These flags are triggered on the rising and falling edges of the interrupt events.
R31 (1Fh)
Comparator
Interrupt Status
R39 (27h)
Comparator
Interrupt Status
Mask
Table 145 External Interrupts
24.3.5
The first-level CODEC_INT interrupt comprises four second-level interrupts for the CODEC. Each of
these has a status bit in Register R31 and a mask bit in Register R39, as defined in Table 146.
These flags are triggered on the rising and falling edges of the interrupt events.
R31 (1Fh)
Comparator
Interrupt
Status
R39 (27h)
Comparator
Interrupt
Status Mask
Table 146 CODEC Interrupts
ADDRESS
ADDRESS
EXTERNAL INTERRUPTS
CODEC INTERRUPTS
15:13
11:8
BIT
BIT
11
10
15
14
13
9
8
CODEC_JCK_DET_L_EINT
CODEC_JCK_DET_R_EINT
CODEC_MICSCD_EINT
CODEC_MICD_EINT
“IM_” + name of respective
bit in R31
EXT_USB_FB_EINT
EXT_WALL_FB_EINT
EXT_BATT_FB_EINT
“IM_” + name of respective bit
in R31
LABEL
LABEL
Left channel Jack detection interrupt.
(Rising and Falling Edge triggered)
Note: This bit is cleared once read.
Right channel Jack detection interrupt.
(Rising and Falling Edge triggered)
Note: This bit is cleared once read.
Mic short-circuit detect interrupt.
(Rising and Falling Edge triggered)
Note: This bit is cleared once read.
Mic detect interrupt.
(Rising and Falling Edge triggered)
Note: This bit is cleared once read.
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Each bit in R39 enables or masks the
corresponding bit in R31. The default
value for these bits is 0 (unmasked).
USB_FB changed interrupt.
(Rising and Falling Edge triggered)
Note: This bit is cleared once read.
WALL_FB changed interrupt.
(Rising and Falling Edge triggered)
Note: This bit is cleared once read.
BATT_FB changed interrupt.
(Rising and Falling Edge triggered)
Note: This bit is cleared once read.
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Each bit in R39 enables or masks the
corresponding bit in R31. The default
value for these bits is 0 (unmasked).
PD, March 2010, Rev 4.2
DESCRIPTION
DESCRIPTION
Production Data
202