WM8352GEB/V Wolfson Microelectronics, WM8352GEB/V Datasheet - Page 182

• Manufacturer Part Number: WM8352GEB/V
• Description: Audio CODECs Audio CODEC plus pwr management
• Manufacturer: Wolfson Microelectronics

Specifications of WM8352GEB/V

• Number Of Adc Inputs: 2
• Number Of Dac Outputs: 2
• Conversion Rate: 48 KSPS
• Interface Type: Serial (2-Wire, 3-Wire, 4-Wire)
• Resolution: 12 bit
• Operating Supply Voltage: 3.7 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: BGA
• Minimum Operating Temperature: - 25 C
• Number Of Channels: 2 ADC/2 DAC
• Supply Current: 260 uA
• Thd Plus Noise: - 83 dB
• Audio Codec Type: Stereo
• No. Of Adcs: 2
• No. Of Dacs: 2
• No. Of Input Channels: 8
• No. Of Output Channels: 6
• Adc / Dac Resolution: 24bit
• Adcs / Dacs Signal To Noise Ratio: 95dB
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

WM8352
20.2 GPIO ALTERNATE FUNCTIONS
w
20.2.1
The following alternate functions are available.
ADCLRCLK
ADCBCLK
CHIP_RESET
CSB
FLASH
HIBERNATE
(Level)
HIBERNATE
(Edge)
HEARTBEAT
/LDO_ENA
L_PWR1
L_PWR2
L_PWR3
MASK
/MR
PWR_OFF
PWR_ON
FUNCTION NAME
ALTERNATE
LIST OF ALTERNATE FUNCTIONS
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
OUTPUT
INPUT /
Alternate Left/Right clock for CODEC ADC digital interface.
When this function is selected, the LRCLK pin supports the
DAC interface only, and GPIO5 provides the ADC digital
interface L/R clock. See Section 12.
Alternate BCLK for CODEC ADC digital interface. When
this function is selected, the BCLK pin supports the DAC
interface only, and GPIO6 or GPIO8 provides the ADC
digital interface BCLK signal. See Section 12.
Logic input to reset the Chip. When this input is asserted,
the chip performs a full reset and re-starts in accordance
with the current config mode settings.
Note that CHIP_RESET_ENA in register R3 should be set
to 1 when using CHIP_RESET as alternative GPIO
function.
3-/4-wire Control Interface Chip Select pin (CSB). Note that
this function is selected automatically on GPIO7 when 3-/4-
wire mode is selected, ie. regardless of the GP7_FN
control field. See Section 11.
Hardware trigger for flash function on ISINKA or ISINKB.
This function is rising edge triggered. The Current Sink
must be in Flash mode, and with the trigger set to GPIO.
See Section 16.
Logic input to place the chip into hibernate. The behaviour
of some components of the WM8352 in Hibernate mode is
configurable. See Section 14.
This “level triggered” input is deemed to be asserted for as
long as it is logic 1 (or logic 0 if the polarity is inverted).
Logic input to place the chip into hibernate. The behaviour
of some components of the WM8352 in Hibernate mode is
configurable. See Section 14.
When the “edge triggered” input is used, Hibernate is
selected when a rising edge occurs (or a falling edge if the
polarity is inverted). After Hibernate has been selected by
this method, a “StartUp” event (see Section 14.3.1) is
required to exit from Hibernate.
Input to Watchdog function, rising edge triggered. See
Section 23.
Enable signal for LDO1. See Section 14.7.4.
Logic input used to place DC-DC Converters or LDOs into
a Low Power state. See Section 14.
Logic input used to place DC-DC Converters or LDOs into
a Low Power state. See Section 14.
Logic input used to place DC-DC Converters or LDOs into
a Low Power state. See Section 14.
Mask input to AUXADC. This input may be used either to
block all inputs to the AUXADC, or to initiate A-D
Conversions. See Section 19.
Logic input used to drive the /RST pin and the /RST and
/MEMRST (GPIO outputs) low. Note that this input has no
other effect on internal circuits. See Section 14.
Logic input signal causes a controlled shutdown of the
WM8352. See Section 14.
Power on input signal from processor (input switching
threshold 1.0V). See Section 14.
DESCRIPTION
PD, March 2010, Rev 4.2
Production Data
182