WM8352GEB/V Wolfson Microelectronics, WM8352GEB/V Datasheet - Page 222

• Manufacturer Part Number: WM8352GEB/V
• Description: Audio CODECs Audio CODEC plus pwr management
• Manufacturer: Wolfson Microelectronics

Specifications of WM8352GEB/V

• Number Of Adc Inputs: 2
• Number Of Dac Outputs: 2
• Conversion Rate: 48 KSPS
• Interface Type: Serial (2-Wire, 3-Wire, 4-Wire)
• Resolution: 12 bit
• Operating Supply Voltage: 3.7 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: BGA
• Minimum Operating Temperature: - 25 C
• Number Of Channels: 2 ADC/2 DAC
• Supply Current: 260 uA
• Thd Plus Noise: - 83 dB
• Audio Codec Type: Stereo
• No. Of Adcs: 2
• No. Of Dacs: 2
• No. Of Input Channels: 8
• No. Of Output Channels: 6
• Adc / Dac Resolution: 24bit
• Adcs / Dacs Signal To Noise Ratio: 95dB
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

WM8352
REGISTER
Register 04h System Control 2
REGISTER
w
ADDRESS
ADDRESS
Hibernate
R5 (05h)
System
BIT
BIT
5:4
2:0
15
7
6
5
4
3
2
REG_RESET_HIB_MODE
WDOG_MODE[1:0]
MEMRST_HIB_MODE
HIB_STARTUP_SEQ
WDOG_HIB_MODE
WDOG_TO[2:0]
RST_HIB_MODE
IRQ_HIB_MODE
HIBERNATE
LABEL
LABEL
DEFAULT
DEFAULT
100
00
0
0
0
0
0
0
0
00 = Disabled
01 = SYS_WDOG_TO interrupt on time-out
10 = WKUP_WDOG_RST interrupt and System
reset on time-out
11 = SYS_WDOG_TO interrupt on first time-out,
WKUP_WDOG_RST interrupt and System reset
on second time-out
Protected by security key. Reset by state
machine. Default held in metal mask.
Watchdog timeout (seconds)
The timer is reset to this value when a
HEARTBEAT signal edge is detected or the host
writes to the watchdog control register.
000 = 0.125s
… (time doubles with each step)
101 = 4s
11x = Reserved
Protected by security key.
Determines what state the chip should
operate in.
0 = Active state
1 = Hibernate state
The register bit defaults to 0, when a reset
happens
Reset by state machine. Default held in metal
mask.
Watchdog behaviour in HIBERNATE state
0 = WDOG disabled in Hibernate
1 = WDOG controlled by WDOG_MODE in
Hibernate
Direction to take when going from Hibernate
state to the Active state.
0 = Hibernate to Active without going through
startup state
1 = Hibernate to Active goes though startup
sequence
Action of the internal register reset signal
when going from Hibernate to Active.
0 = Do a register reset when leaving the
hibernate state.
1 = Do not do a register reset when leaving
the hibernate state
/RST pin state in hibernate mode:
0 = Asserted (low)
1 = Not asserted (high)
IRQ pin state in hibernate mode
0 = Normal operation
1 = Forced to indicate there is no IRQ
/MEMRST (Alternative GPIO function) pin
state in hibernate mode
0 = Asserted (low)
1 = Not asserted (high)
DESCRIPTION
DESCRIPTION
PD, March 2010, Rev 4.2
REFER TO
REFER TO
Production Data
222